Title of Topic : T 1 - Advanced Packaging
Description : Flip-chip and wire-bond packaging, embedded passives and actives on substrates, 3D System in Packaging, etc.
Chair : Navas KHAN, Freescale KL, Malaysia
navaskhan@freescale.com
Co-Chair : Rainer Dudek, Fraunhofer ENAS, Germany
rainer.dudek@enas.fraunhofer.de
Members : Vetrivel Periasamy GANESH, Infineon Technologies, Singapore
Aditya Kumar, GLOBALFOUNDRIES, USA
Jean-Charles SOURIAU, LETI, France
Vempati SRINIVAS, Institute of Microelectronics, Singapore
C.S. Foong, Freescale KL, Malaysia
Florian Bieck, International Rectiffier, Wales
Bok Eng CHEAH, Intel Microelectronics Sdn. Bhd, Malaysia
KIM Hyoung Joon, Samsung Electro-Mechanics (SEMCO), Korea
Jatinder Kumar, Semtech, Malaysia
Title of Topic : T 2 - TSV/Wafer Level Packaging
Description : Wafer level packaging ( Fan in / Fan out ), embedded chip packaging, 2.5D/3D integration, TSV, Silicon & Glass interposer, RDL, bumping technologies, etc.
Chair : Dr. YOON Seung Wook, Statschippac LTD, Singapore
seungwook.yoon@statschippac.com
Co-Chair : Dr. Mark Huang, Suzhou SPEED Semiconductor Technology Pte Ltd), China
mark_huang@speed-hz.com
Members : Mr. Ranjan Rajoo, GLOBALFOUNDRIES, Singapore
Dr. CHEN Kuoming, UMC, Taiwan
Dr. GAURAV Sharma, TSMC, Taiwan
Mr. YANG Seung Taek, SK Hynix Semiconductor, Korea
Mr. KIDA Tsuyoshi, MGC, Japan
Dr. Lee Jaesik, Qualcomm Technologies, Inc, USA
Mr JIN Yong Gang, Apple Computer Singapore, Singapore
Dr. Mingliang Huang, Dalian University of Technology, China
John Hunt, ASE, USA
Rozalia BEICA, Yole, Chief Technology Officer, France
Thorsten Meyer, Infineon AG, Germany
Yann Guillou, Semi Europe
Title of Topic : T 3 - Interconnection Technologies
Description : Au/Ag/Cu/Al Wire-bond / Wedge bond technology, Flip-chip & Cu pillar technology, solder alternatives (ICP, ACP, ACF, NCP, ICA), Cu to Cu, Wafer level bonding & die attachment (Pb-free) etc.
Chair : David HUTT, Loughborough University
D.A.Hutt@lboro.ac.uk
Co-Chair : Liming SHEN, Kulicke & Soffa, Singapore
lshen@kns.com
Members : Horst CLAUBERG, KnS
Wei FAN, Singapore Institute of Manufacturing Technology, Singapore
Hong Meng HO, STATS ChipPAC, Singapore
James HOW, Singapore
Poi Siong TEO, Infineon Technologies Asia Pacific, Singapore
John LAU, ASMT
Yew Cheong MUI , Advanced Micro Devices, Singapore
Nga Phuong PHAM, IMEC, Belgium
Teck Tiong TAN, STATS ChipPAC, Singapore
Daquan YU, Chinese Academy of Science, China
Jack XIONG, Qorvo, Singapore
Tanemasa ASANO, Kyushu University
Title of Topic : T 4 - Emerging Technologies
Description : Packaging technologies for MEMS, biomedical, optoelectronics, Internet of things, photo voltaic, printed electronics, wearable electronics, Photonics, LED, etc.
Chair : Kripesh VAIDYANATHAN, ITE, Singapore
vkripesh@gmail.com
Co-Chair : Martin OPPERMANN, Dresden University of Technology, Germany
martin.oppermann@tu-dresden.de
Members : Perceval COUDRAIN, STMicroelectronics, France
Andreas FIX, Robert Bosch GmbH, Germany
Matthias HUTTER, Fraunhofer Institute for Reliability and Microintegration, Germany
Toni MATTILA, Aalto University Espoo, Finland
James E MORRIS, Portland State University, USA
Nga Phuong PHAM, IMEC, Belgium
Wolfgang REINERT, Fraunhofer Institute for Silicon Technology, Germany
Thomas ZERNA, Dresden University of Technology, Germany
Riko Imade, Singapore MIT Alliance for Research and Technology, Singapore
Title of Topic : T 5 - Materials & Processes
Description : Materials and processes for traditional and advanced microelectronic systems, MEMS, solar, green and biomedical packaging.
Chair : Dr C.H. TOH, Applied Materials, Singapore
ch_toh@amat.com
Co-Chair : Dr Won Kyoung CHOI, STATS ChipPAC Ltd, Singapore
wonkyoung.choi@statschippac.com
Members : Prof. Robert GAO , National Taiwan University, Taiwan
Jun DIMAANO, United Test & Assembly Center Limited, Singapore
Prof. Chee Lip GAN, Nanyang Technological University, Singapore
Prof. Sungdong KIM, Seoul National University of Science & Technology, Korea
Dr Kim Shyong SIOW, University Kebangsaan Malaysia, Malaysia
Alvin LEE, Brewer Science, Taiwan
Prof. Changqing LIU, Loughborough University, UK
Prof. Young-Bae PARK, Andong National University, South Korea
Dr Lim Chong SIM, Intel Technolgy Sdn Bhd, Malaysia
Prof. Chuan Seng TAN, Nanyang Technological University, Singapore
Dexter REYNOSO, Heraeus, Singapore
Bart VANDEVELDE, IMEC, Belgium
Vempati Srinivasa RAO, IME, Singapore
Dr Jun WEI, Singapore Institute of Manufacturing Technology, Singapore
Dr Loke Yuen WONG, Applied Materials, Singapore
John OVISO, Advanpack Solutions Pte Ltd, Singapore
Chin-Yu (Max) LU, Siliconware Precision Industries Ltd, Taiwan
Dr Suan Hui PU, University of Southampton, Malaysia
Title of Topic : T 6 - Electrical Modeling & Simulations
Description : Power plane modeling, signal integrity analysis of substrate/package.
Chair : Wui Weng Wong, AMD
wui-weng.wong@amd.com
Co-Chair : Mihai Rotaru, U. of Southampton, U.K.
mr@ecs.soton.ac.uk
Members : Aoyagi Masahiro, AIST, Japan
Weerasekera Roshan, IME, Singapore
Xiang Yin Zeng, Avago Technologies
Chee Parng Chua, Molex
Engin Ege, San Diego State University , USA
Fujiang Lin, USTC, China
Jianyong Xie, Intel Assembly & Test Techology Development (ATTD), Pheonix
Chetan Verma, Freescale, India
Title of Topic : T 7 - Mechanical Modeling & Simulations
Description : Thermo-mechanical, moisture, fracture, fatigue, vibration, Shock and drop impact modeling, Chip-package interaction, etc.
Chair : Andrew TAY, National University of Singapore, Singapore
mpetayao@nus.edu.sg
Co-Chair : Shan GAO, GLOBALFOUNDRIES, USA
Shan.Gao@globalfoundries.com
Members : Ephraim Suhir, Portland State University, USA
Daoguo Yang, Guilin University of Electronic Technology, China
Suresh SITARAMAN, Georgia Institute of Technology, USA
Kuo Ning CHIANG, National Tsing Hua University, Taiwan
Leo ERNST, Ernst Consultant
Steve GROOTHUIS, Micron, USA
Yong LIU, Fairchild, USA
Juergen Auersperg, Fraunhofer ENAS, Germany
Wei Zhou, Micron, Singapore
Azhar Aripin, On Semi, Malaysia
Eric Yong, Infineon Technologies Asia Pacific, Singapore
Premachandran CS, GLOBALFOUNDRIES
Xiaowu ZHANG, Institute of Microelectronics, Singapore
Christopher Bailey, University of Greenwich, UK
Rathin MANDAL, Advanced Micro Devices Singapore, Singapore
Title of Topic : T 8 - Thermal Characterization & Cooling Solutions
Description : Thermal modeling and simulation, component, system and product level thermal management and characterization
Chair : Rathin MANDAL, Advanced Micro Devices Singapore, Singapore
Rathin.Mandal@amd.com
Co-Chair : Marta RENCZ, Mentor Graphics - MicReD, Hungary
marta_rencz@mentor.com
Members : Wataru NAKAYAMA, Therm Tech International, Japan
Yogendra JOSHI, Georgia Institute of Technology, USA
Sandeep TONAPI, Anveshak Technology and Knowledge Solutions, USA
Justin A. WEIBEL, Purdue University, USA
Yong Jiun LEE, CAD-IT Consultants (Asia) Pte Ltd, Singapore
Yong Sheng CHUA, DSO National Laboratories, Singapore
Melvin TAN, Nanyang Technological University, Singapore
Edwin TEO, Nanyang Technological University, Singapore
Hengyun ZHANG, Shanghai University of Engineering Science, China
Marcin JANICKI, Lodz University of Technology, Poland
Yong HAN, Institute of Microelectronics (A-star), Singapore
Title of Topic : T 9 - Quality & Reliability
Description : Component, board and system level reliability assessment, Interfacial adhesion, accelerated testing, failure characterization, etc.
Chair : Tong Yan TEE, SMARTS Enterprise, Singapore
tongyan.tee@gmail.com
Co-Chair : Alfred YEO, Infineon, Singapore
Alfred.Yeo@infineon.com
Members : Masazumi AMAGAI, Texas Instruments, Japan
Christian BIRZER, Infineon Technologies, Germany
JF Jo CAERS , Philips Applied Technologies, The Netherlands
Liqiang CAO, Chinese Academy of Science, China
Xuejun FAN, Lamar University , United States
Yi-Shao LAI, ASE, Taiwan
Stefano MARIANI, Politecnico di Milano, Italy
Keith NEWMAN, Hewlett Packard, United States
Hong Wan NG, Micron, Singapore
Shaw Fong WONG, Intel, Malaysia
Chong Chin Hui, Micron, Singapore
Stevan Hunter, Onsemi
Title of Topic : T 10 - Wafer/Package level & TSV Testing & Characterization
Description : High-speed test architectures and systems design, 2.5D & 3D test methodologies, probe card design, package-test interaction, high-throughput testing etc.
Chair : Bruce KIM, City University of New York
bruce.kim@ieee.org
Co-Chair : Sang-Bock Cho, University of Ulsan, South Korea
sbcho@ulsan.ac.kr
Members : Prem Chahal, Michigan State University
Sungho KANG, Yonsei University, Korea
En-Xiao LIU, Institute of High Performance Computing, Singapore
Dr. Sock-Ho Noh, Andong National University, Korea
Abhilash Goyal, Oracle (Sun Microsystems), USA
Xiaoxiong Gu (Kevin), IBM T.J. Watson Research Center, NY, USA
Li Li, Cisco Inc
Nanju Na, IBM
Seungbae PARK, The State University of New York at Binghamton
W. L. CHONG, Advanced Micro Devices, Singapore
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