Invited speakers

On-Chip Embedded Cooling of Power and Logic Components



Avram Bar-Cohen, PhD, IEEE/EPS President Elect (2018-2019)

Principal Engineering Fellow, Raytheon Corporation – Space & Air Borne Systems, Rosslyn, Virginia, USA


Abstract: Thermal packaging technology has been a key enabler in the development of today’s microelectronic systems and is responsible for much of the benefit that we derive from miniaturization, higher performance, lower cost and greater reliability of today’s electronic “widgets.” A review of thermal packaging over the first 70 years of the Information Age will reveal a relentless “inward migration” of cooling technology from room ventilation and air-conditioning, to cabinet cooling, to component cooling with heat sinks and cold plates, and to today’s efforts to address on-chip hot spots and near-junction thermal transport. Attention will then be devoted to a discussion of Gen3 thermal management technologies relying on intra- and interchip microfluidic cooling, use of diamond substrates, and on-chip thermoelectric coolers to implement the emerging “embedded cooling” paradigm.

Bio: Dr. Avram Bar-Cohen is an internationally recognized leader in thermal science and technology, an Honorary Member of ASME and Life Fellow of IEEE, currently serving as a Principal Engineering Fellow at Raytheon Corporation – Space and Airborne Systems, on leave from the University of Maryland. His publications, lectures, short courses, and research, as well as his US government and Professional service in ASME and IEEE, have helped to create the scientific foundation for the thermal management of electronic components and systems. His current efforts focus on embedded cooling, including on-chip thermoelectrics, diamond substrates, and two-phase microchannel coolers for high heat flux electronic and photonic components in computational, radar, and directed energy systems.

Bar-Cohen is a former Editor-in-Chief of the IEEE CPMT Transactions and serves on the Board of Governors of the CPMT Society. He has represented the Society as a Distinguished Lecturer for more than 15 years and is the President-elect of the CPMT Society. He recently completed his service as a Program Manager in the Microsystem Technology Office at the Defense Advanced Projects Agency in Virginia and had earlier served as Department Chair of Mechanical Engineering and Distinguished University Professor at the University of Maryland – College Park.

In 2014 Bar-Cohen was honored by the IEEE with the prestigious CPMT Field Award and had earlier been recognized with the CPMT Society’s Outstanding Sustained Technical Contributions Award (2002). Among other awards, Bar-Cohen received the Luikov Medal from the International Center for Heat and Mass Transfer in Turkey (2008) and ASME’s Heat Transfer Memorial Award (1999), Edwin F. Church Medal (1994), and Worcester Reed Warner Medal (1990).

In addition to serving as the Editor-in-Chief of WSPC’s Encyclopedia of Thermal Packaging and the co-editor of the Advanced Integration and Packaging book series, Bar-Cohen has co-authored Dielectric Liquid Cooling of Immersed Components (WSPC, 2013), Design and Analysis of Heat Sinks (Wiley, 1995), and Thermal Analysis and Control of Electronic Equipment (McGraw-Hill, 1983), and has edited/co-edited 28 other books in this field. He has authored/co-authored more than 400 journal papers, refereed proceedings papers, and chapters in books and has delivered some 100 keynote, plenary and invited lectures at major Conferences, Symposia, and college campuses throughout the world.

  

Enhanced Bonding Technology for Hybrid Integration in 3D Packaging Technology


Guilian Gao, L.W. Mirkarimi, G. Fountain, S. Arkalgud, Liang Frank Wang and Bongsub Lee

Xperi, 3025 Orchard Parkway, San Jose, CA 95129, USA

Abstract: Continuous miniaturization of electronic devices is driving the growth of 3D packaging in multiple markets segments including mobile, Internet of Things (IOT), and automotive. System in Package (SIP) and Micro-Electro-Mechanical Systems (MEMS) applications are proliferating multiple markets. Enhanced functionality with component size reduction are expected in the next generation products while the average sales price (ASP) is falling. Additionally, the automotive market demands highly accurate, low temperature or vibration drift adding additional pressure for cost-effective solutions. Die shrink is a natural choice for cost reduction for both SIP and MEMs. Streamline manufacturing with one bond technology that serves multiple applications is attractive for driving down cost. The dielectric bonding technology (ZiBond) and hybrid bonding technology (Direct Bonding Interconnect or DBI) are platform technologies, which offer higher yield, lower cost of ownership and the potential of electrical interconnect through the bond line. The DBI technology forms a dielectric-to-dielectric bond at room temperature and ambient pressure and then establishes metal-to-metal connection (usually Cu-to-Cu bond) by a low temperature batch annealing (150 – 300oC).


This talk includes an analysis of the SIP and MEMS market trends and requirements, a brief introduction of the hybrid bonding technology in wafer-to-wafer and die-to-wafer applications. The challenges and advantages of ZiBond and DBI technology compares the conventional bond techniques in MEMs. The bond strength and hermeticity of ZiBond prototype cavity packages are studied. ZiBond and DBI technologies offer a bonding process with superior bond strength of 120—180 MPa, compared to 10-15 MPa reported for anodic bonding. Other MEMs bonding techniques, Eutectic and glass frit, are also evaluated. The electrical performance and assembly yield data for prototypes built with die-to-wafer (D2W) are discussed.


D2W technology for SIPs is attractive as the bonding surface is simply an extension of the dielectric and metal layer of the die back end of line (BEOL), so the conventional thermal compression bonding (TCB) of solder micro bumps is no longer required. Compared to the low throughput of microbump TCB process, DBI offers an elegant solution with short bond dwell times (~0.1 seconds for dielectric bonding) and batch anneal processes, which significantly enhances the overall throughput. The bond interface contains only Cu and dielectric, with no solder or other adhesives.  Consequently, the thermal-mechanical stress from the interconnect is reduced, thus enabling further die thickness reduction without compromising performance. Another significant breakthrough is the drastic increase of interconnect density. Interconnect pitch for micro bump TCB is currently around 40µm, or 625 interconnects per mm2 and further pitch reduction is extremely difficult. However, with the DBI technology, the interconnect pitch scalability follows the lithographic and bonder alignment capability to micron-level pitches. This technology is capable of greater than 1 million interconnects per mm2 for pitch scaling in X-Y dimension. The combination of ultrahigh interconnect density in the X-Y dimension and ultrathin die in Z direction enables chip designer to re-configure ICs from 2D design to 3D design to achieve  significant power reduction and electrical performance enhancement.    Furthermore, the technology is fully compatible with BEOL wafer fabrication processes and can reduce the overall cost of ownership. 

Bio: Guilian Gao received her Ph.D. in Materials Science from University of Cambridge, U.K, her M.S. in Corrosion and Protection from University of Manchester, U.K and her B.S. in Materials Science and Engineering from Beihang University, China. Dr. Gao has 27 years of experience in electronics packaging technology development, materials, processes and reliability engineering. She is currently a Principal Engineer in 3D Technology at Xperi Corp. in San Jose, CA. Prior to her Xperi assignment, she was a Staff Engineer and Program Manager at Tessera Inc. Before joining Tessera, she was a Senior Technical Specialist at Ford Motor Co. and was awarded the Henry Ford Technology Award.  Dr. Gao holds 29 US patents and more than 30 publications.

 

Packaging of Integrated Silicon Photonic devices:  Electrical, Optical, Thermal Challenges and Applications


Jun Su Lee, Senior Packaging Researcher, Photonics Packaging group, Tyndall National Institute

Abstract: As increasing demands for integrated photonic devices in data centers, telecommunications and sensors, various silicon photonic devices are being developed. Accordingly the Si-photonic modules are designed with various packaging prototype structures in development. The optimization of packaging configurations is indispensable for Si-photonic devices to be productized or to be tested out of the research labs. Although the packaging structures and requirements of Si-photonic devices can be diverse by their applications, Si-photonic packaging can be simplified into the three parts of electronics, optics and thermal management, and all of these three factors must to be comprehensively considered for planning the Si-photonic packaging. In this presentation, we are going to discuss the challenges of photonic packaging through the cases of Si-photonic packaging developments at Tyndall National Institute. Technologically as for electronic, optical packaging and thermal management respectively, this presentation contains fine pitch Cu pillar flip-chip bonding, optical fiber alignment on photonic integrated chips, and thermal modeling using a FEM simulation. Lastly, Si-photonics packaging service at Tyndall National Institute and PIXAPP program of open-access photonic integrated circuit (PIC) assembly and packaging pilot line will be briefly introduced.

Bio: Jun Su Lee received his PhD degree in microsystems (in Electronic Engineering) from Imperial College London, UK in 2006. He moved to Korea and worked at Amkor Technology Korea as a senior researcher to develop electronics packaging from 2006 to 2010. And then he worked as a principal researcher at Samsung Advanced Institute of Technology (SAIT) for leading a project of medical X-ray detector development from 2010 to 2012. After that, he worked at Institute of Microelectronics in Singapore as a scientist II to develop MEMS integration from 2012 to 2013. Currently he is working at the Tyndall National Institute in Ireland as a senior packaging researcher in the Photonics Packaging Group from 2013. He has been leading EU funded research projects and the development projects of industrial companies. His research activities focus on flip-chip bonding and optical packaging for optoelectronic devices in Si-photonics.


Abstract: To be submitted



Bio: Chan Pin was appointed as Senior Vice President of K&S’s AP-Hybrid, Electronics Assembly, Wedge Bonders and Consumables Business Lines in December 2016. He joined K&S in 2014 as Vice President of Wedge Bonders business group and has successfully turnaround the business and led the team to higher growth by diversifying the business into the battery bonding market.

Chan Pin is a technology industry veteran with more than 24 years of engineering and operations experience in the semiconductor and electronics industry. He started his career first as a Process and Test Engineer at Motorola Pagers and Cellular group and pioneered multiple factories in Asia before advancing to the role of Manufacturing Manager at Flextronics. In 1999, Chan Pin joined KLA-Tencor and held a number of diverse positions, including Senior Technical Director of Engineering and General Manager of Strategic Business Unit in Greater China. Chan Pin then pioneered the efforts of starting the MEMS factory in Singapore when he became the Vice President of Sales and General Manager at Form Factor. Most recently, he was the Global President & CEO at Everett Charles Technologies, managing and leading in test and probe technologies.

Chan Pin received his bachelor's degree in Electrical Engineering and Computer Science from the State University of New York at Buffalo and a master's degree in Business Administration from the University of Leicester, United Kingdom. A Singaporean national, he is a military reserve (National Service, NS) Brigade 2nd in Command of a combined arms division.

 

UV Laser Releasable Temporary Bonding Materials for Advanced Packaging technologies by Kenzo Ohkita, Ph.D.


JSR Corporation, Yokkaichi, Mie, Japan, kenzou_ookita@jsr.co.jp

Abstract: As Moore’s law is reaching its limitations, the innovative evolutions of advanced electronic packages are required. Semiconductor devices that deploy 2.5D/3D integration and fan-out packages have progressed to satisfy these requirements in the recent decade. For 3D packaging, device wafers are usually thinned down to less than 100 μm for reducing total packaging thickness and the electrical resistance. On the other hand, for fan-out packaging manufacturing, silicon or glass support wafers are necessary as temporary substrates for building up re-distribution layers (RDLs) or for fabricating chip embedded mold wafers.Temporary bonding (TB) technology is essential for realizing such high performance electronic packages. In this technology, the thin and fragile silicon wafers or fan-out wafer level packages (FO-WLPs) are enabled to be handled by fixing onto a rigid carrier. To release the wafers from the carrier, a UV laser release system is used and its process is very promising because of high-throughput manufacturing without mechanical stress at room temperature. The UV lase with highly energy density has advantages in terms of low heat damage and can directly induce photochemical reaction of carbon-carbon covalent bonds within the order of a nanosecond. The UV Laser release system also provide wider process window relative to the other releasing methods. This technology can be applied not only for silicon or mold wafers but also for large substrates in panels form.


In this presentation, an appropriate design for a material-pair which is adhesive and releaser layer used in temporary bonding process will be described. The material-pair should survive exposure to various chemical and thermal stresses through photolithography, electroplating, vapor deposition, and etching process. The adhesive with high rigidity at high temperature to support and protect device wafer is necessary. The release layer with high UV laser absorption rate to give selective decomposition of TB layer and low transmittance rate to minimize the potential damage to the device wafer are exhibited. Also, the chemical resistance and thermal resistance at 250 oC or even higher are required to apply the wide spread of device applications.

Bio: Dr. Kenzo Ohkita is a manager of Advanced Electronic Materials Laboratory at JSR Corporation. He is currently responsible for material development for 3D packaging technology, especially temporary bonding / debonding (TBDB) materials and photo-definable dielectrics. He received PhD in Chemistry at Osaka University (Japan, 1994). After joining JSR, he has 20 years’ experience in research and development of various materials; functional polymers design and their large volume production, high heat-resistant resins, photoresist for display applications, and materials for printed electronics applications.


Wafer Bonding – An Enabling Technology for 3DIC, MEMS, BSI CIS, SOI, RF Filters, and More


Eric Pabo , Business Development Manager, MEMS of  EV Group

Abstract: Wafer bonding is one of the enabling technology for most 3DICs (3D Integrated Circuits),  MEMS (Micro Electro Mechanical Systems), MOEMS (Micro Optical Electro Mechanical Systems), BSI (Back Side Illuminated Image Sensor), CIS (CMOS Image Sensors), SOI wafers, heterogeneous integration, multi junction PV  (Photo Voltaic) cells, high performance RF (Radio Frequency) filters, microfluidics and wafer level optics.  This presentation will highlight the often hidden process of wafer bonding by reviewing the primary aligned wafer bonding processes for 3DICs, MEMS, BSI CIS, and heterogeneous integration.   The bonding processes reviewed will include direct bonding, plasma activated direct bonding, hybrid bonding, solder/ eutectic bonding, and thermo-compression bonding.

Bio: Eric Pabo is the Business Development Manager for MEMS for EV Group, prior to this he was the Bonding Applications Engineer for EV Group in North America. He has been with EV Group for over 11 years, has 34 years of experience in electronics manufacturing, with 18 years of experience in wafer bonding and wafer level packaging at Hewlett Packard, Agilent Technologies and EV Group.Eric is a registered Professional Engineer in the state of Colorado, is a Six Sigma Black Belt and has a Mechanical Engineering Degree from Colorado State University. Eric occupies any spare time he may have with his hobby of photography


Temporary Bonding Materials for Fan-out Packaging Processes


Abstract: Pending

Bio: Ram Trichur is the Director of Business Development at Brewer Science. In his current role, he oversees world-wide business development for advanced packaging materials. He received his B.Engg degree in Electrical Engineering from Bharathidasan University, India and his M.S degree in Electrical Engineering from University of Cincinnati. He has received 3 patents and is the author of more than 30 publications. Prior to joining Brewer Science he was a microfluidics research engineer at Bruker Corporation in Billerica, MA.


Reliability Assurance: A Semiconductor Supplier’s Perspective


By Stevan G. Hunter

Abstract: This presentation will explore and highlight the current reliability space from the perspective of the semiconductor supplier.  Semiconductor components and ICs have generally had good reliability lifetimes, and manufacturers are still driven in their relentless efforts to eliminate defects to improve yield and reliability.  The concepts of Design for “X” (DfX) are easier said than done in the supplier’s cost- and schedule-constrained environment.  Reliability test and qualifications costs, schedule, and effectiveness are continually being scrutinized due to increasing customer expectations and more stringent industry standards.  Lean six sigma practices are widespread in semiconductor manufacturing.  Semiconductor reliability improvements are typically made by “guardbanding” or tightening process or test limits, not through a fundamental improvement that eliminates the “physics of failure”.  Field returns data is important, but often difficult to obtain in sufficient detail, and is clouded with processing by the sequence of customers after parts are out of the semiconductor supplier’s control.  Customers have the responsibility to preserve the built-in reliability of semiconductors, especially by preventing EOS and ESD in their operations.  The risks of previously unknown or untested “physics of failure” mechanisms increase as devices continue to shrink, new processes are introduced, and integration escalates with 3-D packaging. 

BiO: Stevan G. Hunter, PhD, is a Member of Technical Staff, for Quality and Reliability, at ON Semiconductor, Phoenix, AZ.  He has 39 years semiconductor industry experience, teaches Lean Six Sigma courses at ON, teaches at BYU-Idaho and Arizona State University as adjunct, and is an adjunct faculty member at the University of Maryland CALCE.  Stevan holds certifications as Six Sigma Blackbelt, Reliability Engineer, and ESD Factory Control Manager.  He is a Senior Member of IEEE and ASQ, member of IMAPS, and serves on the EOS/ESD Association Industry Council and various committees. 


Highly accurate TSV, PWB and FO-PLP wirring fabication by plasma dry processes for interface.


By Yasuhiro Morikawa, Manager, ULVAC

Abstract: High-performance CPU and large capacity memory for AI / DL, edge- computing and high density packaging technology, are indispensable to realize the next-generation IoT cloud society. High-density packaging technologies such as 3D-IC, 2.5 / 2.1D and 2D scheme basing on PCB (Print Circuit Board) substrate are among key technologies to satisfy the requirements from the both smart semiconductor devices and smart functional devices such as heterogeneous integration. ULVAC has been continuously developing manufacturing solutions for TSV, Embedding and Fan-Out (PWB, WLP / PLP) packaging. In this presentation, buildup multilayer, RDL, TSV technologies solutions consisting of plasma etching / ashing and PVD (Physical Vapor Deposition) sputtering to make the high density interconnection package will be introduced.

 Bio: Yasuhiro Morikawa" is currently the manager of development of dry etching / ashing and polymer coating technologies for 2D, 2.5D, and 3D packaging applications within the Institute of Semiconductor and Electronics Technologies at ULVAC. And, he has been also development for the deep quartz etcher for Opt and Bio-MEMS applications.

Yasuhiro joined ULVAC in 1997. He earned his Master. in Electrical engineering from the University of Toyo in 1997. And, he received a Ph.D. in Material Engineering from the University of Tokyo in 2003.

Yasuhiro is a member of the Japan Society of Applied Physics, Committee of International Symposium on Dry Process (DPS) , and Member of The Japan Institute of Electronics Packaging(JIEP)

 


Advanced eWLB FOWLP: Enabling Integrated Packaging Solutions



Seung Wook Yoon, Ph.D, STATS ChipPAC Ltd. 10 Ang Mo Kio Street 65 Techpoint #04-08/09 Singapore 569059, Seungwook.yoon@statschppac.com

Abstract: New and emerging applications in the consumer and mobile space, the growing impact of the automotive, Internet of Things (IoT) and wearable electronics (WE) and the complexities in sustaining Moore's Law have been driving many new trends and innovations in advanced packaging technology. And the advancement of silicon scaling to 7/10 nanometer (nm) in support of higher performance, bandwidth and power efficiency in mobile devices is pushing the boundaries of emerging packaging technologies to smaller packaging designs with finer line/spacing as well as improved electrical performance and highly integration.  Advanced embedded Wafer Level Ball Grid Array (eWLB) technology provides a versatile platform for the semiconductor industry’s technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations.

This paper reports developments that advanced eWLB FOWLP technology, including integration of multi-die, discretes, embedded passives and crystals.  This will also discuss the adoptions and new features available for automotive, mobile, IoT and WE. This advanced technology is well designed for MEMS/sensors SiP modules as well as thin, highly integrated packaging. Innovative 2.5D/3D packaging features will be also introduced with the merits and characterization data for specific applications. 

Various test vehicles have been designed and fabricated to demonstrate these low profile solutions for mobile, portable and wearable electronics. The test vehicles have ranged from medium to large sizes and 0.4mm bottom ball pitch. To enable higher interconnection density and signal routing, packages with multi-layer redistribution (RDL) and fine line/width spacing are fabricated and implemented on the eWLB platform. Successful reliability characterization results are reported as an enabling technology for highly integrated miniaturized, low profile and cost-effective solutions.  

 Bio: Dr. YOON is currently working as director of Advanced Products & Technology Marketing, STATS ChipPAC Pte. Ltd in Singapore.  His major interests are for Advanced Packaging and Integration Technology including eWLB/Fanout WLP, SiP and integrated 3D IC packaging. Prior to joining STATS CHIPPAC LTD, He was deputy lab director of MMC (Microsystem, Module and Components) lab, IME (Institute of Microelectronics), A*STAR, Singapore. ”YOON” received Ph.D degree in Materials Science and Engineering from KAIST, Korea. He also holds MBA degree from Nanyang Business School, Singapore. He has over 250 journal papers, conference papers and trade journal papers, and over 20 US patents on microelectronic materials and electronic packaging. Currently working as technical committee member of various international packaging technology conferences, EPTC, ESTC, iMAPS, IWLPC and SEMI.

 

10 Golden Rules of Chip- Package- Board Interactions

By E.Napetschnig, Infineon Technologies Austria AG ; Villach Austria

Abstract: As they strive to reach even better technology solutions in even faster time the semiconductor industry engineers of today tend to forget about basic principles. The ten golden rules aim to support the engineers to find the best solution by questioning the right way. As the rules are very basic every engineer in the semiconductor industry can apply them. Most experienced technical experts have come together and formulated the rules, thus, best results are granted as the worst failure paths are included. The most experienced engineers of Infineon Technologies AG came together and formulated the rules to enable a faster time to market while implementing highly reliable stable processes in the end. On the first sight some of the rules are very basic technical common sense, but too often the basic principles are overseen during project planning and will lead to issues, delays and even fail and cancelation of the projects. This list of ten golden rules can be print out on one sheet, placed on every table of a semiconductor engineer and can act as a reminder to respect the most basic principles of material science, mechanics, thermodynamics and electronics while keeping an eye on the productivity. Omitting the 10 golden rules is helping to decrease the complexity of the available process and thus allow approaching the highest quality requirements that are given by the current market. 

 

Bio: Evelyn Napetschning received her Ph.D. and Masters degrees in Technical Physics from Vienna University of Technology, Austria in 2008 and 2003 respectively. Dr. Evelyn has 11 years of experience in semiconductors frontend/backend process integration. She is currently a Senior Staff Engineer at Infineon Technologies. She is also holding Process Block Catalogue Integration Champion and Complexity Manager position within the TEX complexity management team, Villach. Dr. Evelyn holds 7 patents to her credit.

 

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