EPTC 2019 Invited Paper Details Download
Topic: Development of multi-chip integration non-molded 2.5D IC Packaging Technology
Dr Chen Wei Chung Curry, Technical Consultant, ASE Global
Recent requirements for 2.5D IC package with high bandwidth and high performance applications is bringing molded and non-molded 2.5D packaging technology innovations into another level. Our production and development experience in non-molded 2.5D devices include 20 × 20 mm2 to 70 × 70 mm2 packages with 2 to 5 chips. Non-molded package has benefits such as cost saving and variable thermal solutions, however the warpage control and stress distribution always become challenges and constraints for larger module hardware. Package design, advanced material selection and process design for stress and warpage control will be illustrated in this presentation. Practical process with reliability results combine with stress simulation data will be discussed as well
Topic : Mechanical simulation and reliability
Prof. Jeffrey Suhling, Professor, Auburn University
Topic: System Packaging Solutions for High Performance Computing in the Era of 5G/IoT
Mr. Shunichi Kikuchi, Vice President, Fujitsu Advanced Technologies Limited
High Performance Computers have been extending the performance in order to computationally solve intensive tasks in various fields, combining a variety of packaging technologies. The transition in their performance can be seen in the past ToP500 lists. The list which discloses High Performance LINPACK (HPL) benchmark scores from No.1 to No.500 is updated twice a year. Through the data analyses of the past ToP500 lists in the past 26 years, several findings and current trends from the viewpoint of system packaging can be shared with audience. With processor packaging trends, high speed interconnects and other promising technologies, a few system packaging solutions will be introduced for future high-performance computing. Moreover, I will also explain about newly prepared measurement methods in order to implement the above system packaging. Finally, I will present a direction of system packaging for the era and beyond, including challenges facing the sustainable development goals.
Topic : Electrical Simulation and Characterization
Dr Gokul Kumar, Principal R&D Engineer, Western Digital
Topic: 3DIC integration technology
Mr. C.S Premachandran, Manager, Globalfoundries (USA)
System level integration on logic and memory has been an important subject to packaging community for mobile and HPC (High performance computing) applications. Recent years, 3DIC integration technology has advanced from substrate level package to wafer level system integration. Wafer level integration leads the semiconductor industry into a new era of system scaling beyond Moore's Law. This talk will give the requirement of reliability aspects on 3D fine pitch wafer to wafer bonding and 2.5D interposer on 65nm technology which is set to go on volume production.
Topic: Cooling of high-power microelectronic components using flow boiling
Prof Yogendra Joshi, Professor, Georgia Institute of Technology
With the continuing trend towards heterogeneous integration, volumetric power densities are likely to increase. Microfluidic two-phase cooling provides a potential solution to achieve high heat transfer capabilities, and high temperature uniformity in the presence of hot spots. This presentation will present an approach for computational simulations of flow boiling for chip cooling, illustrated with multiple examples. Also presented will be experimental validations of the computations.
Topic: Effects of trace element on electromigration of flip chip interconnect between Cu Pillar and Sn-Bi alloy system
Mr Murayama Kei, Research and Development, Shinko Electric Japan
From environmental issues, economics and technical points of view, the demands for low temperature soldering is increasing year by year. Sn - Bi solders are powerful candidate materials to realize its demands. We investigated effects of surface finish and trace element on electro-migration of flip chip interconnection between Cu-pillar and Cu or Cu/Ni/Au pad using Sn-Bi solder alloy system by Electron backscattered diffraction (EBSD) and Electron probe micro analyzer (EPMA). We introduce that Au, Pd and Ni trace element influence on electro-migration resistance. Au, Pd atoms play a role of accelerating diffusion Ni into Cu6Sn5. When Au and Pd atoms were small, Inter-metallic compounds growth at Cu pillar side is limited. On the other hand, in case of existing small amount of Ni atoms in solder, they form dense scallop type (Cu,Ni)6Sn5 layer at substrate pad and acted as an effective barrier against diffusion from Cu or Ni pad.
Topic: Evolution of Fault Isolation Techniques for Product Failure Analysis
Dr Goh Szu Huat, Deputy Director, GlobalFoundries Singapore
The mission of global fault localization is to narrow the physical inspection area to as small and accurate as possible. This is vital to increase the chance of failure analysis success. Against the backdrop of chip scaling, advanced packaging architectures as well as the prevalence of more complex failure types, conscientious efforts to examine and refine custom fault isolation techniques is crucial to achieve this mission. This talk describes the overall trends in both die and package-level fault isolation techniques. The underlying challenges and motivations that drive these enhancements will also be discussed.
Topic: Opto-electronic test and characterization
Dr Sia Choon Beng, FormFactor Inc, Singapore
By 2030, to satisfy the increasing demands for cloud computing and services for various emerging applications such as artificial intelligence, genomics revolution and video transcoding etc, the energy consumption of all data centers is projected to be about 20% of the earth’s total energy produced! Silicon photonics with optical fibers is the potential candidate to replace copper interconnects within data centers as it drastically reduce power consumption, cost and size of the optical transceiver modules. By utilising the mature silicon CMOS processing technologies, silicon-based photonics products can be fabricated cost-effectively with well-established production solution. In this invited talk, an optimized and automated setup for optoelectronic test and characterization will be presented. The setup is currently used for known-good-die tests prior to die stacking which is crucial for effective 3DIC heterogeneous integration and packaging of silicon-based optical transceivers. This talk also presents possible solutions to establish challenging correlations of wafer-level tests to the final product tests - as most silicon photonics chips utilize edge couplers to transfer light in and out of the chip in IC packages while most of the commercially available wafer-level test solutions require grating couplers for wafer top-side light transfer.
Topic: Micro-interconnects: Signal Integrity in 5G Applications
Dr Murali Sarangapani, Heraeus Materials Singapore Pte Ltd
This presentation deals with two aspects on micro-interconnects in semiconductor packaging. First, recent developments in wire bonding, soldering, sintering primarily designed for low electrical resistivity are reported. Second, these wire-bonded, sintered and soldered structures satisfy low loss in transmitting wide bandwidth signals in 5G applications are discussed. In bonding wire technology, bare and palladium coated copper wires have positioned themselves in high volume replacing gold bonding wires successfully. Alloyed silver wires are used in LED. Gold coated silver wires are studied for memory applications using cascade bonding method. Low temperature bismuth-tin solders have been examined for the last few decades and currently are popular in the usage to reduce warpage (zero) and electrical power consumption. The reflow temperature of these solders are aimed to be less than 190°C. Sintering with nanoparticles reduces process temperature by rapid necking. Using bi-modal electrically conductive powder particles and composite materials, Heraeus-innovation team explores sintered interconnects to process with low reflow/sinter temperatures. In addition, the sintered interconnects possess low insertion losses with good signal and power integrity. The talk concludes with a challenge to researchers to develop new interconnect materials without limiting the boundaries between electrical resistivity and high-volume production, while still aiming to innovate micro-interconnects with unified performance that blends signal integrity with low insertion loss and low electrical/thermal resistivity.
Topic in Package Reliability
Dr Daniel Rhee Min Woo, Program Manager, Samsung Korea
Topic in Advanced Packaging
Dr. Yu-Po, Wang, Director, SPIL Corporate R&D Centre
Mr Favier Shoo, Yole Development
In this digital new age, advanced nodes do not bring the desired cost-benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. Hence, advanced packaging represents an opportunity to increase product value offering advantages down both the scaling and functional roadmaps. This presentation will focus on arguably one of the most exciting advanced packaging platforms – Fan-Out Packaging. In 2019, key players from all different business models have Fan-Out packaging solutions in the market. Fan-out packaging technology is not only a bridge to chip-package interaction (CPI) mismatch in pitch size, but is also a viable solution for heterogeneous integration of functionalities, now potentially used for mmWave 5G and Cloud data server applications. Fan-out success is evidently defined by the well-established “core” standard FO market and the startling market penetration of high-density FO (HDFO), which brought Fan-Out Packaging into a whole new level of spotlight.
Topic: Virtual prototyping for electronic packaging development, dream or reality?
Dr Jing-En Luan, R&D Manager, ST Electronics
New product or module development is very challenging nowadays. The development cycle time is shortening, and reliability requirement is higher and higher. CAE is widely used in package development. Simulation become more and more important in new product development. Industry is pursuing virtual prototyping for new product. However, the accuracy of the models and simulation results is one of the biggest limitations that virtual product development engineers have today. in the product or package development team, there is always challenging and argument how to use simulation results. Engineers from different background have different opinions. The PM/ EPM may have difficulty to understand or believe the results.
In the presentation, the author will share the product/package development flow. The key milestones during development. And how modeling supports it for virtual prototype and key limitation. The author will share examples on each key area to bridge the gap between simulation and experiment or reality. Virtual prototyping is possible with improvement in key area while designer/simulation engineer/material test / engineer work together. It make a higher level of integration not only engineering but also manpower.
Topic: What is new for the fast learning of IC Reliability - Advanced Defect Learning, Package Structural Testing, & Reliability modelling by HPC
Mr Xue Ming, Lead Principal Failure Analysis, Infineon
IC package reliability fails are occurred typically with time, loading stress, and environmental stress, which is often escaped from manufacturing test. Package structural fault is a common early deviations cause reliability failures, for example, wire near short, lifted ball bond, die crack. To learn and implement control in manufacturing process for package structural fault is slow as limited detection and take time with conventional approach. A number of new approach are in our horizon, Package structural fault test, Advanced defect learning, and Reliability modelling with High performance computing. This talk will present to you the state of the art and leading development in this topic.