Professional Development Course

The conference program includes Half day Professional Development Courses (PDC) Please choose one course during your registration. 

PDC 1: Power Electronics Packaging for Automotive Application 

PDC 2: Fan-Out Wafer/Panel-Level Packaging and Heterogeneous Integrations 

PDC 3: Reliability Mechanics and Modeling for IC Packaging 

PDC 4: Antenna-in-Package (AiP) Technology for Millimeter Wave Systems 

PDC 5: Co-Design/Modeling and Additive Manufacturing for Electronics Packaging 

Professional Development Course (PDC) 01

Title: Power Electronics Packaging for Automotive Application

Instructor: Prof. Mervi Paulasto-Kröckel; Aalto University

Abstract

This course provides an overview what kind of power technologies, packaging concepts and materials are currently used in different products from power semiconductors to power modules, and what are the prevailing trends and challenges in automotive applications.

The course will first review the application areas of different power semiconductor technologies. Then different power packages and interconnect technologies used in automotive applications will be introduced.  Power module packaging concepts will be explained, requirements and possible concepts for e-mobility are presented. The lecture will then proceed to reliability issues in power packages and modules. In this context, robustness validation and design for reliability is covered. Finally, new developments in terms of materials and their implications on performance, thermal management and reliability will be discussed. 

Mervi Paulasto-Kröckel is of Electrical Engineering in Finland. She completed her Helsinki University of Technology in 1995. Prior to joining Aalto University end of 2008, she worked over 12 years in the automotive semiconductor industry in various R&D and management positions. Her group Electronics Integration and Reliability focuses on advanced materials and interconnect technologies for MEMS/NEMS and power electronics, as well as multi-material assemblies behavior under different loads and their characteristic failure mechanisms. Prof. -Kröckel has over 110 international publications in of microelectronics packaging and compatibility of dissimilar materials. She is Distinguished Lecturer of IEEE EPS.


Professional Development Course (PDC) 02

Title: Fan-Out Wafer/Panel-Level Packaging and Heterogeneous Integrations

Instructor: Dr. John H Lau; Unimicron Technology Corporation

Abstract

Fan-out wafer/panel-level packaging (FOW/PLP) has been getting lots of since TSMC used their InFO to package the application for the iPhone 7. In this lecture, the following topics will be presented and discussed: (1) Formation of Fan-out Wafer-Level Packaging (FOWLP): FOWLP Chip-first (die face-down), FOWLP Chip-first (die face-up), and FOWLP Chip-last (RDL-first), (2) Fabrication of Redistribution Layers (RDLs): Polymer and ECD Cu + Etching, PECVD and Cu damascene + CMP, Hybrid RDLs, and ABF/LDI and PCB Cu-plating + Etching, (3) Warpages: Kinds of Warpages and Allowable of Warpages, (4) Reliability of FOWLP: Thermal-Cycling Test, Thermal-Cycling Simulations, Drop Test, and Drop Simulations, (5) TSMC InFO: InFO-PoP, InFO_AiP/RF-Chip Driven by 5G, and InFO for HBM, (6) Samsung PLP: PoP for Smart watches and SiP SbS for Smartphones, (7) Formation of Fan-out Panel-Level Packaging (FOPLP): PCB + SAP, PCB + LDI, PCB + TFT-LCD, and PCB/ABF/SAP + LDI, (8) Wafer vs. Panel: Application Ranges of FOWLP and FOPLP, and Critical Issues of FOPLP, (9) Fan-Out RDL for High Performance Applications: STATSChipPac’s FOFC-, ASE’s MedieTed’s FO-RDLs, Samsung’s Si-Less RDL Interposer, and TSMC’s InFO_oS, and (10) Trends in FOWLP and FOPLP.

John H Lau: With more than 38 years of R&D and manufacturing experience in semiconductor packaging, John H Lau has published more than 480 peer-reviewed papers, 30 issued and pending US patents, and 20 textbooks on, e.g., Fan-Out Wafer-Level Packaging (Springer, 2018) and Heterogeneous Integrations (Springer 2019). John is an elected IMAPS Fellow, ASME Fellow and has been an IEEE Fellow since 1994.


Professional Development Course (PDC) 03

Title: Reliability Mechanics and Modeling for IC Packaging - Theory, Implementation and Practices

Instructor: Prof. Fan; Lamar University

Abstract

This course aims to present a comprehensive coverage of reliability mechanics and modeling under various loading conditions. In addition to the introduction of fundamentals, the course contents are arranged in four modules. Module 1 covers modeling under thermal loading, such as problems related to of thermal expansion or non-uniform temperature distribution. Module 2 deals with the modeling under mechanical loading, such as mechanical bending and/or drop impact. Module 3 will cover modeling under humidity/moisture loading for moisture related problems, such as failures in soldering as well as under HAST and Module 4 will introduce multi-physics modeling that involves the combined thermal, moisture, electrical, and mechanical loading. Theoretical foundation and the best practices for numerical simulations will be covered. future perspective in reliability mechanics and modeling will be discussed. Course outline includes: 1. Fundamentals of stress analysis and computational modeling for IC packaging; 2. Reliability issues and modeling under thermal loading; 3. Reliability issues and modeling under mechanical loading; 4. Reliability issues and modeling under moisture/humidity loading; 5. Reliability issues and modeling under combined loading – multi-physics modeling

is a Mary Ann and Lawrence E. Faust endowed chair professor in the Department of Mechanical Engineering at Lamar University, Beaumont, Texas. He received his Ph.D. solid mechanics from Tsinghua University, Beijing, China in 1989. His interests and research lie in the areas of modeling and reliability in microelectronics packaging. Dr. extensive experience as with Intel Cooperation, Philips Research, and the Institute of Microelectronics (IME), Singapore. Dr. Fan received the Outstanding Sustained Technical Contribution Award in 2017, and the Exceptional Technical Achievement Award in 2011 from CMPT. He is an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology, and an IEEE Fellow and Distinguished Lecturer. He serves as chair, co-chairs, and committee members of various conferences such as ECTC, EPTC, ESTC, EuroSimE, ICEPT, ESREF, and EMPT. He has published more than 250 papers, including 4 books, over 100 journal papers, many book chapters, and numerous conference papers.


Professional Development Course (PDC) 04

Title: Antenna-in-Package (AiP) Technology for Millimeter Wave Systems

Instructor: Prof. Y. P. Zhang; Nanyang Technological University 

Abstract

Antenna-in-Package (AiP) technology is an antenna solution technology that realizes an antenna or antennas in or on an integrated circuit package that can carry a radio or radar die or dies to be mounted on a system printed circuit board. technology has been widely recognized as the mainstream antenna and packaging technology for millimeter-wave (mmWave) applications such as 60-GHz radio and gesture radar, 79-GHz automotive radar, and 28-GHz New Radio.  In this course, I shall first introduce how AiP technology has been developed, as we know today. Then, I shall cover four aspects of AiP technology including design, fabrication, testing, and applications. Next, I shall give two AiP examples with one designed for 60-GHz radio in a low-temperature co-fired ceramic process and the other designed for 5G New Radio in a fan-out wafer level packaging. Finally, I shall draw the conclusion and identify to further advance technology.

Y. P. ZHANG is a full Professor with the School of Electrical and Electronic Engineering at Nanyang Technological University, Singapore, a Distinguished Lecturer of the IEEE Antennas and Propagation Society (IEEE APS), a Member of the IEEE APS Paper Award Committee. Prof ZHANG was a Member of the IEEE APS Field Award Committee (2015-2017), an Associate Editor of the IEEE Transactions on Antennas and Propagation (2010-2016), and the Chair of the IEEE Singapore MTT/AP joint Chapter (2012), leading the Chapter to win the Best Chapter Awards from the IEEE APS and the IEEE Singapore Section (2013), respectively. Prof ZHANG has published and accepted numerous papers. He holds 7 US patents. Prof Zhang was awarded a William Visiting Fellowship by the University of Hong Kong (2005). He was selected by the Recruitment Program of Global Experts of China as a Distinguished Scholar affiliated to Shanghai Jiao Tong University (2012). He has been elevated to the grade of IEEE Fellow for contributions to integrated antennas and subsurface radio since 1 January 2010.


Professional Development Course (PDC) 05

Title: Co-Design/Modeling and Additive Manufacturing for Electronics Packaging

Instructor: Prof. Chris Bailey, University of Greenwich

Abstract

Advanced electronics packaging for system and heterogeneous integration of electronic, electrical, optoelectronic, biological, and sensing components is estimated to grow significantly over the next ten years. These advanced packaging technologies (wafer-level packaging, 3D-IC, embedding, heterogeneous integration) and the recent use of additive manufacturing technologies pose challenges for designers in terms of die-package-system interactions (electrical, thermal, mechanical) that need at the early stage of package design to ensure the final package meets customer requirements in terms of performance and reliabilityThis course is broken down into three modules. Module (1) will provide an overview of the latest trends in advanced packaging and additive manufacturing technologies and key electrical, thermal, mechanical, and reliability issues that need to be addressed by electronic packaging designers. Module (2) will detail the latest trends and developments in co-design and multi-physics modeling tools for electronic packaging engineers for both advanced packaging and additive manufacturing technologies. Module (3) will provide real examples of co-design and multi-physics modeling for wafer-level packaging, 3D-IC, and embedding technologies as well as additive manufacturing processes such as ink-jet and aerosol jet technologies. Finally, the course will detail the challenges that need to be addressed by such design tools for these technologies in terms of materials data characterization for future simulations.

Chris Bailey is Professor of Computational Mechanics & Reliability at the University of Greenwich, London, UK. He has over 20 years R&D and Design, Modelling and Simulation experience in electronics packaging and associated manufacturing technologies. He has published over 300 journal and conference papers; consulted with over 60 companies worldwide; and led a number of UK, US, and European funded research projects into the use of design, modeling and simulation tools for electronic packaging technologies. Chris is also chair of the roadmap chapter on modeling and simulation in the Heterogeneous Integration Roadmap (HIR). He is also President-Elect of the IEEE Electronics Packaging Society; Chapter Chair of the UK & EPS and Reliability Societies; and Associate Editor of IEEE Transactions on Components, Packaging.














Prof. Mervi Paulasto-Kröckel



















Dr.John H Lau



















Prof. Xuejun Fan

























Prof. Y. P. Zhang


















 

Prof. Chris Bailey


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