EPTC Highlights

Important Dates

Dates

Notification of acceptance

22th Aug 2018

Submission of manuscript

30th Sep 2018


Special 20th Anniversary Program


Keynotes and Invited Presentations by experts:

·         Ivor Barber, VP, AMD, USA.

·         David McCann, VP, Globalfoundries, USA.

·         Dr Avram Bar Cohen, Raytheon Corporation, USA.

·         Dr. Stevan G Hunter, On Semiconductor, USA.

·         Dr. Bill Chen, Fellow, ASE Group, USA.

·         Prof. Robert Kao, National Taiwan University.

·         Prof. Jeffrey Suhling, Auburn University, USA.

·         Dr. Evelyn Napetschnig, Infineon Technologies.

·         Mr. Sam Karikalan, Broadcom Inc., USA.

·         Mr. Paul Werbaneth, Intevac.

                And many more

 

·     BoG Meeting


First time ever IEEE EPS Board Of Governors meeting held outside USA. Many packaging experts who are members of BoG will be participating in the conference program.

 

Conference Banquet in S.E.A. Aquarium


Fine dining at a stunning and memorable backdrop with marine animals sighted through a panoramic window to the ocean.

 




List of Invted Presentations




1.      “Emerging NAND Memory Packaging Challenges”

Dr. Gokul Kumar 


2.“Interface Pattern Void Analysis in Face to Face Hybrid Wafer Bonding”

Dr Soon-Wook Kim


3.“Basic considerations to define a proper frontend backend interaction for die bonding”

Dr. Evelyn Napetschning 


4. "Technology Trends for Large Area Panel Level Packaging”

Tanja Braun 

 

5." Jump the Learning Curve: Looking Beyond Cluster Tools for Barrier/Seed Layer PVD”

Paul Werbaneth 

 

6.“Low temperature interconnect technology using Sn-Bi alloy system for high performance packages”

Kei Murayama 


 7.“Packaging for Performance Scaling”

Sam Karikalan 

  

8.“Microfluidic Electroless Interconnection Process for Low-Temperature, Pressureless Chip-stacking”

Dr. Robert Kao 


  9.“Advanced Interconnect Material Solutions for 5G Market”

Dr. Yuan Yuan Zhou 

 

10.“ESD, EOS and AMR”

Dr. Stevan Hunter


Professional Development Courses (PDC) Instructors





Introduction to fan-out wafer-level packaging, Dr. Beth Keser – Intel Corporation.


·     Advanced integrated circuit design for reliability, Dr. Richard Rao – Microsemi Corp, USA


       3D SIP For ASIC and DRAM Integration, Dr Li Li- Cisco Systems Inc.


       Understanding flip chip technology and its applications, Mr. Eric Perfecto – GLOBALFOUNDRIES.


·      Introduction to 3D interconnect and packaging technologies, Prof. Sarah Kim – Seoul National University of Science and   Technology.


·     Power Electronic Packaging Reliability, Materials, Assembly and Simulation - Dr Ning Cheng Lee, Dr Yong Liu, Prof Sheng Li


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