Advanced System Integration Technology Trend

Abstract:

HPC and AI/ML technologies have profound impact on human society. Semiconductor technology plays critical roles to realize these. Recently progress in generative AI drives AI/ML’s impact to a new height. Higher performance computing with ever-increasing model size requires much higher level of computation performance, communication, and memory bandwidth, all at higher energy efficiency (EE). Advanced nodes Si scaling is expected to continue providing higher performance computing with higher EE. Advanced heterogeneous system integration technologies, however, can provide even more values than before for the HPC and AI/ML systems. This can be achieved by the scaling up of classical(microelectronics)-based system integration, advanced photonics-based system integration, as well the two integrated.

Speaker’s Biography

Doug Yu is a Vice President of TSMC R&D and TSMC Distinguished Fellow responsible for system integration technology pathfinding. Previously Doug led TSMC Cu/Low-K technology development and established industry’s first wafer level system integration technology platform TSMC 3DFabricTM including CoWoS®, InFO and SoICTM. These technologies start new semiconductor technology trends and set industry standards. Doug also pioneered TSMC COUPE (Composite Universal Photonic Engine), a photonics integration technology. Prior to TSMC, Doug worked with AT&T Bell Labs. He received Ph.D. degree in Materials Engineering from Georgia Institute of Technology, Atlanta, GA. Dr. Yu received the IEEE Rao Tummala Award, the IEEE EPS Microelectronics Manufacturing Award, and the President Science Prize, Taiwan. He is an IEEE Fellow and a member of the National Academy of Engineering. Doug has made numerous invited/keynote/plenary speeches in international conferences and published over 150 papers to elevate the profile of system integration technology.

2.5D/3D Heterogeneous Integration for Silicon Photonics Engines

Abstract

As, per lane, data rates continue to rise, optical interconnects are getting closer and closer to the processor to minimize overall system power consumption. To this end, to design what is essentially a processor with optical IO, higher levels of integration are needed to build optical engines. We will discuss various integration approaches that have been taken to accomplish very compact optical interconnect systems.

Speaker’s Biography

Dr. Radha Nagarajan is Senior Vice President and Chief Technology Officer of Marvell’s Optical and Copper Connectivity Group. In this role, he manages the development of the company’s optical platform technology and products. Radha joined Marvell from Inphi, where he served as the Senior Vice President and Chief Technology Officer of Platforms. Prior to joining Inphi, he was a Fellow at Infinera where he was focused on the design, development, and commercialization of large scale photonic integrated circuits.  Dr. Nagarajan has been awarded more than 230 US patents and is a Fellow of the IEEE, Optica (formerly OSA) and IET (UK). He was awarded the 2006 IEEE/LEOS Aron Kressel Award and the 2022 IPRM Award in recognition of breakthrough work in the development and manufacturing of large scale photonic integrated circuits. He holds a B.Eng. from the National University of Singapore, M.Eng. from the University of Tokyo, and Ph.D. from the University of California, Santa Barbara, all in Electrical Engineering.

Advanced Packages Enriching Heterogeneous Integration

Abstract

Advanced IC Packages are typically Ball Grid Array (BGA) and Flip-Chip (FC) based with various structures to meet demanding high performance chiplet computing needs. This presentation will discuss innovative BGA, Fan-Out with FC technologies – FOCoS, plus 2.5D / 3D packages, describing how the integration needs are optimized with higher precision, effective layout with enhanced electrical signal and power performance, very essential for new generation AI server, data center, 5G and latest edge computing applications.

Speaker’s Biography

Dr. C.P.Hung currently holds the position of Vice President, Corporate R&D, at ASE Group. Based in Taiwan, he leads teams responsible for next-generation product development featuring integrated technologies, as well as a broad range of advanced chip, package, and system integration solutions. During his tenure, Dr. Hung has performed a variety of management roles at ASE, including VP of Corporate Design, VP of Central Engineering & Business Development and VP of Logistic Services Integration. He holds 180 patents encompassing IC packaging structure, process, substrate, and characterization technology. He has also published over 105 conference and journal papers. Dr. Hung has been the SEMICON Taiwan PKG & TEST Committee Chair since 2013, and currently Co-Chair since 2021. He is also a member of the IEEE EPS Board of Governor since 2019.

Will Advanced Packaging Save Moore’s Law?

Abstract

Dimensional scaling in leading edge logic technology is becoming increasingly challenging. This presentation will review critical issues associated with logic technology and examine system and technology co-optimization as a viable path to extend Moore’s law through adoption of advanced packaging technology. We will discuss fundamental equipment capabilities that must be established in the coming years to enable true 3D integration of chiplets.

Speaker’s Biography

Yang Pan joined Lam Research in 2003 and is currently Corporate Vice President focusing on defining and enabling of technology and product roadmap for advanced packaging. He was the head of Advanced Technology Development group and Global Product Group CTO in Lam Research headquarter. He was also the head of Lam Research China from 2003 to 2014. Before joining Lam, he held various positions at Chartered Semiconductor Manufacturing Ltd from 1994 to 2003, including Vice President of Fab3 and Fab1 operations, GM of Silicon Manufacturing Partners (SMP), and process integration and device engineering manager in the Research and Development Group. Yang Pan received his Ph.D. degree in Electrical Engineering from Delft University of Technology, the Netherlands. He was a technical committee member of VLSI Technology Symposia. He was an adjunct associated professor at National University of Singapore. He received Lee Kuan Yew Postdoctoral Fellowship from National University of Singapore in 1992. Yang Pan has been awarded more than 60 U.S. patents and published more than 40 papers in international journals and conferences.

Dr. Douglas Yu, TSMC