Challenges and Opportunities in Heterogeneous Integration

Dr. Ravi Mahajan, Intel Fellow, Assembly and Packaging Technology Pathfinding for future silicon nodes

ABSTRACT: Heterogeneous Integration is a powerful and crucial enabler for the continued growth of computing performance.  Advanced packaging technologies are critical enablers of Heterogeneous Integration (HI) because of their importance as compact, power-efficient platforms. This talk will focus on the tremendous opportunities in different application environments and focus on the projected evolution of advanced packaging architectures.  Specific examples showing how product implementations take advantage of these technologies to provide an unprecedented level of performance will be used to describe the challenges and opportunities in developing robust advanced package architectures.

Biography: Ravi Mahajan is an Intel Fellow responsible for Assembly and Packaging Technology Pathfinding for future silicon nodes. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives. He has led Pathfinding efforts to define Package Architectures, Technologies and Assembly Processes for multiple Intel silicon nodes, including 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Ravi joined Intel in 1992 after earning his Ph.D. in Mechanical Engineering from Lehigh University. He holds the original patents for silicon bridges that became the foundation for ' 'Intel's EMIB technology. His early insights have led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques for thermo-mechanical stress model validation. His contributions during his Intel career have earned him numerous industry honors, including the ' 'SRC's 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME, the 2019 ”Outstanding Service and Leadership to the IEEE” Awards from IEEE Phoenix Section & Region 6 and most recently the 2020 Richard Chu ITherm Award and the 2020 ASME EPPD Excellence in Mechanics Award. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and is currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. He has long been associated with ' 'ASME's InterPACK conference and was Conference Co-Chair of the 2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE.  He was elected to the National Academy of Engineering in 2022 for contributions to advanced microelectronics packaging architectures and their thermal management.

New Directions and Challenges in the Packaging of AR/VR Hardware

Dr. Raj Pendse, Director of Si Packaging at Meta Reality Labs

ABSTRACT: This presentation will focus on the new trajectory for Si Packaging technology set by the emergence of AR/VR hardware and advanced wearable computing. Taking a look back, we see the phenomenal evolution in computing hardware from mainframe computers in the 50’s to personal computing in the ’80s and now to handheld computing in the form of the ubiquitous smartphone – we believe the next major step in that evolution will be wearable computing in the form of a novel, hands-off and all-day wearable AR/VR devices like AR glasses. These devices will continue the remarkable journey of miniaturization and power/performance carved out by their predecessors.

We will discuss the complex array of Si and Packaging technologies that lie under the hood of such devices, spanning the three areas of Augmented Reality Processing (ARP), Display and Imaging (D&I) and Low-energy Wireless (LW) communication. We will demonstrate unique approaches that combine advanced packaging technologies like flip chip, fan-out wafer-level packaging and TSV, often within the same package. Finally, we will discuss the challenges created by the need to spawn new ecosystems, such as heterogeneous integration and fabrication methods that often fall in the grey zone between Foundry and OSAT.

Biography: Dr. Raj Pendse is the Director of Si Packaging at Meta Reality Labs and leads the development of advanced Si/Packaging solutions for AR/VR hardware. Raj was previously Vice President of Package Engineering at Qualcomm and played various leadership roles in Package development at STATS ChipPAC, Hewlett-Packard Labs and National Semiconductor.

Raj’s work spans the gamut from Packaging of microprocessors, ASIC’s and GPU’s for High-Performance Computing to Packaging solutions for logic and analog devices that find use in Mobile platforms and Consumer hardware. His most recent focus has been on 3D and Wafer Level Packaging for AR/VR hardware. Raj completed his BS in Materials Science from IIT Bombay with Top in Class honors and his Doctorate in Materials Science from UC Berkeley.

Materials Engineering Innovations to address Next-Gen Electronics Packaging Challenges

Dr. Sundar Ramamurthy, VP & GM Advanced Packaging, Applied Materials

ABSTRACT: Heterogenous design and integration have been referred to as the fourth stage of the evolution of Moore’s Law, as it enables simultaneous improvements in power, performance, and area-cost. The expected performance and cost improvements from traditional Moore’s Law scaling have slowed down as we reach the limits of cost-effective monolithic scaling across most computing architectures. As Moore’s law slows down, die size needs to increase to improve performance, becoming one of the key limiters for yield and at risk of hitting the reticle limit. Heterogeneous designs enable us to overcome the critical issue of reticle limit by separating functionality across two or more chiplets, enabling us to increase performance and reduce die size and cost. Advanced packaging ensures high bandwidth and power-efficient interconnects between chiplets using technologies such as through-silicon vias and hybrid bonding to enable the heterogenous system to operate with comparable efficiencies as monolithic integrated circuits.

The need for high bandwidth connectivity drives new packaging technologies which can deliver higher interconnect density and smaller interconnect pitch. Hybrid bonding needs new dielectrics and optimized copper grain morphology which enable low-temperature processing. Tuning the CMP process for optimal bond surface profiles can improve the efficiency of the bonding process. Experimental validation, along with atomistic modelling, can guide the selection of materials and process conditions to speed up development and reduce cost.

Panel-level packaging offers the ability to reduce cost by moving to larger formats. However, new challenges for handling large substrates must be addressed. Speeding up yield-learning and addressing defect sources requires increased inspection and monitoring for known-good die. This presentation will discuss the materials challenges and engineering innovations that are enabling the advances required for the next generation of electronic packaging.

Biography: Dr Sundar Ramamurthy is responsible for Applied’s business in packaging, specialty semiconductors and epitaxy markets. In this role, Sundar leads an integrated team across the company to fuel growth in some of the fastest-growing markets in the semiconductor industry.

Sundar previously led the metal deposition business unit, delivering growth in physical vapor deposition and share gains in atomic layer and chemical vapor deposition of thin metal films. His team commercialized several new products to solve critical transistor and interconnect challenges to enable device scaling by introducing new materials into volume manufacturing. Sundar has served in various leadership roles, including general management of the front-end products business unit.

Sundar holds a Ph.D. in Materials Science and Engineering from the University of Minnesota and a Bachelor of Technology degree in metallurgical engineering from the Institute of Technology, Banaras Hindu University. He has authored or co-authored over 30 technical papers in peer-reviewed journals and has more than 30 patents granted or pending. Sundar serves on the External Advisory Board for the department of Chemical Engineering and Materials Science at the University of Minnesota. He is also an active mentor with the Miller Centre at Santa Clara University for accelerating social enterprises.

Dr. Ravi Mahajan

Dr. Raj Pendse

Dr. Sundar Ramamurthy