Keynote Talks

Title : Advanced Package FAB solutions for Next Generation Devices

Speaker: Seung Wook Yoon, Corporate VP/Head of Team of Package Technology Strategy and Planning, Samsung Electronics

Dr YOON is currently the Corporate VP and Head of Team of Package Technology Strategy and Planning, Samsung Electronics. Before joining Samsung, he was director of group technology strategy, STATS ChipPAC, JCET Group. He also worked as a deputy lab director at the Institute of Microelectronics, A*STAR, Singapore. ”Yoon” received a Ph.D degree in Materials Science and Engineering from KAIST, Korea. He also holds an MBA degree from Nanyang Business School, Singapore. He has over 300 journal papers, conference papers, trade journal papers, and over 20 US patents on microelectronic materials and electronics packaging. He has served as a technical committee member of various international packaging technology conferences, EPTC, ESTC, iMAPS, IWLPC and SEMI. 

Abstract: SAMSUNG Advanced Package FAB solutions provide complementary and extended solutions with complete supply chain management including Fanout WLP, Panel level PKG, 2.5D as well as 3D Integration. Currently higher computing power and memory bandwidth are the major requirements of Al and GPU, accelerators and network devices. These demands lead to the adoption of the advanced packaging technologies to increase bandwidth density, thermal performance and to improve electrical performance with shorter interconnection length. 3D TSV technologies provide high bandwidth density within a limited footprint. For HPC applications, 2.5D and 3D technologies are employed for cloud and artificial intelligence (AI). High-performance chip size continues to increase up to one reticle size and the cost of the leading-edge silicon node is recently soaring. So various chiplet packaging solutions, such as 2D, 2.5D and 3D are necessary to develop fine pitch interconnection evolutions with the Cu hybrid bonding or fine pitch microbump bonding process. In this presentation, the above-mentioned advanced package FAB solutions are to be introduced and discussed in terms of challenges and opportunities for emerging high-end computing and mobile processor platforms. Furthermore, Fanout WLP, RDL interposer, high-performance 3D SIP and Integrated Stacked Capacitor (ISC) are introduced. 

Title : Future directions for 3D Integration technologies, enabling further electronic system-level scaling benefits

Speaker: Eric Beyne, Senior Fellow, VP R&D, Director 3D System Integration, IMEC

Dr.Eric Beyne obtained a degree in electrical engineering in 1983 and the Ph.D. degree in Applied Sciences in 1990, both from the Katholieke Universiteit Leuven, Belgium.  Since 1986, he has been with IMEC in Leuven, Belgium, where he has worked on advanced packaging and 3D interconnect technologies. Dr. Beyne is currently IMEC Senior Fellow, VP R&D, and Program Director of imec’s 3D System Integration program.

Abstract: As electronic systems become more complex and CMOS scaling becomes more specialized, a variety of heterogenous device technologies will be required to realize them. The highly successful system-on-chip (SOC) design methodology of complex systems will need to evolve to an effectively “3D-SOC” heterogeneous system design methodology. This requires a functional partitioning of the systems in separate die (“chiplets”) that require high bandwidth, low latency, and low energy 2.5D and 3D integration technologies to “reconstitute” the systems.  A broad range of possible technologies are available to realize this. Proposing a hierarchical view of the 3D interconnect fabric, we define a 3D interconnect technology landscape, that extends from the package-level all the way to the transistor level, spanning eight orders of magnitude in 3D interconnect density.  This Landscape is highly dynamic, as each technology has its own roadmap and scaling roadmap. This presentation will cover imec’s contributions to this 3D interconnect scaling technology in the areas of TSV integration, die-to-wafer, wafer-to-wafer stacking.

Title: Packaging Materials as a Key Enabler for Future Megatrends 

Speaker : Klemens Brunner, President, Heraeus Electronics

Dr. Klemens is president of Heraeus, a leading packaging materials supplier in the electronics industry.  Before 2018, he was head of the Marketing & Sales department of Heraeus Electronics. He began his career at Philips Research in the Netherlands, where he worked on LEDs technology development and Philips business group Automotive Lighting in product marketing. He joined Lumileds (formerly a division of Philips) in San Jose, USA as general manager of the business unit Automotive LED and general manager Automotive Lighting Asia Pacific, where he was based in Hong Kong.  Klemens Brunner has a PhD in physical chemistry from the University of Vienna.

Abstract: 5G Communications, Renewable Energy generation and Electric Vehicles are megatrends that not only impact our daily lives, but also bring significant changes to the entire electronics semiconductor packaging industry. Continuous miniaturization of semiconductor devices requires more advanced packaging to deliver better electrical performance, smaller footprint and higher reliability. Heraeus Electronics will discuss how materials innovations enable such requirements through breakthroughs in the packaging of devices and address the various technology challenges, from ever-shrinking interconnects for System-In-Package (SiP), to stringent reliability requirements for Power & Automotive electronics.

EPTC 2021 Platinum Sponsor

Keynote Speakers

Seung Wook Yoon 

Eric Beyne

Klemens Brunner