PDC courses
PDC |
Title |
Instructor |
1 |
Fan-Out,
Chiplet, and Heterogeneous Integration Packaging |
John H
Lau (Biography) |
Unimicron
Technology Corporation, Taiwan |
||
2 |
Flip
Chip Interconnects |
Eric
Perfecto (Biography) |
IBM
Research, USA |
||
3 |
Co-Packaged
Si Photonics: Opportunities and Challenges |
Amr S
Helmy (Biography) |
University
of Toronto, Canada |
||
4 |
Design-on-Simulation
Technology for Advanced Packaging Reliability Life Prediction |
Kuo-Ning
Chiang (Biography) |
National
Tsing Hua University, Taiwan |
||
5 |
Automotive
Electronics Reliability – Challenges and Opportunities |
Pradeep
Lall (Biography) |
Auburn
University, USA |
Fan-Out,
Chiplet, and Heterogeneous Integration Packaging |
|
Course Objective: There are two parts of this lecture:
First part of the course convers the Fan-out and chiplet design for 1 hour
followed by second part of course covers the Heterogeneous integration
packaging for 2 hours. For fan-out, the following topics will be presented
and discussed: (1) Fan-out wafer/panel-level Packaging; (2) Formation of
FOWLP, (a) Chip-First (Die Face-Down), (b) Chip-First (Die Face-Up), and (c)
Chip-Last (or RDL-First); (3) Fabrication of Redistribution Layers (RDLs),
(a) Polymer and ECD Cu + Etching, (b) PECVD and Cu Damascene + CMP, (c)
Hybrid RDLs, and (d) Laser drill + LDI + PCB Cu-plating + Etching; (4)
Formation of FOPLP, (a) Chip-First (Die Face-Down), (b) Chip-First (Die
Face-Up), and (c) Chip-Last (or RDL-First); (5) TSMC InFO, (a) InFO-PoP, and
(b) InFO_AiP Driven by 5G mmWave; (6) Samsung WLP/PLP, (a) PoP for Smart
Watches and (b) SiP SbS for Smartphones; (7) Warpages, (a) Warpage Types and
(b) Allowable of Warpages; (8) Reliability of FOWLP and FOPLP, (a)
Thermal-Cycling Test, (b) Thermal-Cycling Simulations, (c) Drop Test, and (d)
Drop Simulations; and (9) Examples, (a) Chip-First Panel-Level Fan-Out
Packaging of Mini-LED for RGB-Display, (b) Chip-Last Panel-Level Fan-Out
Packaging of Application Processor Chipset, (c) 2.3D IC Integration with
Chip-First Fan-Out RDL-Interposers, and (d) 2.3D IC Integration with
Chip-Last Fan-Out RDL-Interposers. Emphasis is placed on the fundamentals and
latest developments of these areas in the past few years. For fan-in
packaging, a six-side molded wafer level package and its reliability will be
presented. The trends of fan-out and fan-in wafer-level packaging will be
discussed. Chiplet is a chip design method and heterogeneous integration is a
chip packaging method. Chiplet design and heterogeneous integration packaging
have been generated lots of tractions lately. For the next few years, we will
see more implementations of a higher level of chiplet designs and
heterogeneous integration packaging, whether it is for cost, time-to-market,
performance, form factor, or power consumption. Course Outline: (1) System-on-Chip
(SoC) and Why Chiplet Design? (2) Chiplet
Design and Heterogeneous Integration Packaging: a. Chip
partition and Heterogeneous Integration b. Chip
split and Heterogeneous Integration c. Advantages
and Disadvantages (3) Lateral
Communication between Chiplets (e.g., Bridges): a. Bridge
Embedded in Build-up Package Substrate b. Bridge
Embedded in Fan-Out EMC with RDLs c. UCIe d. Hybrid
Bonding Bridge (4) Chiplet
Design and Heterogeneous Integration Packaging: a. Multiple
System and Heterogeneous Integration with Package Substrate (2D IC
Integration) b. (Multiple
System and Heterogeneous Integration with Thin Film layer on the Package
Substrate (2.1D IC Integration) c. Multiple
System and Heterogeneous Integration with TSV-less (Organic) Interposer (2.3D
IC Integration) d. Multiple
System and Heterogeneous Integration with Passive TSV-Interposer (2.5D IC
Integration) e. Multiple
System and Heterogeneous Integration with Active TSV-Interposer (3D IC
Integration) (5) Summary (6) Potential
R&D Topics in Chiplet Design and Heterogeneous Integration Packaging. Who Should Attend? If you (students, engineers, and
managers) are involved with any aspect of the electronics industry, you
should attend this course. It is equally suited for R&D professionals and
scientists. Each attendee will receive more than 300 pages of lecture notes. Instructor’s Biography |
|
John H
Lau, with more than 40 years of R&D and manufacturing experience in
semiconductor packaging has published more than 515 peer-reviewed papers (375
are the principal investigator), 40 issued and pending US patents (25 are the
principal inventor), and 23 textbooks (all are the first author) such as
Fan-Out Wafer-Level Packaging (Springer, 2018), Heterogeneous Integration
(Springer, 2019), Semiconductor Advanced Packaging (Springer, 2021). and
Chiplet Design and Heterogeneous Integration Packaging (Springer, 2023). John
is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been
actively participating in industry/academy/society meetings/conferences to
contribute, learn, and share. |
|
Flip
Chip Interconnect by Eric Perfecto |
|
Course Objective: This course will cover the
fundamentals of all aspects of flip chip assembly technologies, including
various type of wafer bumping technologies, solder joint formation,
non-solder joints and assembly considerations. The course is divided into two
sections. The first section focuses on the key steps of flip chip assembly
technologies and their associated equipment and materials. The second section
dives into the depth of the fundamental aspect of flip chip technology. It
will detail the various interconnect technologies used in today’s flip chip
assembly. It will discuss the various under-bump metallurgy (UBM) fabrication
methods (electroplating, electroless plating and sputtering) and solder
depositions methods (electroplating, ball drop, IMS, and solder screening).
The course will cover the various failure modes related to bumping, such as
barrier consumption, Kirkendall void formation, non-wets, BEOL dielectric
cracking, etc. Special focus of the course will be on fine pitch
technologies, mainly u-Pillar and Hybrid bonding. Course Outline: · Introduction
to Flip Chip Technologies · Flip
Chip Technologies: Mass Reflow vs Thermal Compression Bonding · Packaging
Technologies · Bumping
Ground Rules · Flip
Chip Under-Bump Metal and Intermetallic · Flip
Chip Solder Deposition Processes · Cu
Pillar Technology · Hybrid
Bonding Who Should Attend: The goal of this course is to
provide the students with a comprehensive understanding of flip chip
fabrication and its use on the various advanced packages. Students are
encouraged to bring topics and technical issues from their past, present, and
future job function for group discussions. |
|
Instructor’s Biography Eric Perfecto has over 40
years of experience working in the development and implementation of C4 and
advanced Si packages at IBM and GlobalFoundries. Eric’s responsibilities
include UBM and Pb-free solder definition for C4 and u-Pillar interconnect,
and yield improvements in C4 and 3D wafer finishing. He holds a M.S. in
Chemical Engineering from the University of Illinois and a M.S. in Operations
Research from Union College. Eric has published over 80 external papers,
including two best Conference Paper Awards and the 1994 Prize Paper Award
from CMPT Trans. on Adv. Packaging. He holds 60 US patents and has been
honored with three IBM Outstanding Technical Awards. Eric was the 57th ECTC
General Chair in Reno, NV, and the Program Chair at the 55th ECTC. Eric is an
IEEE Fellow, an EPS Distinguish Lecturer and EPS VP of Education. |
|
Co-Packaged
Si Photonics: Opportunities and Challenges |
|
Course Objective and
Outline: This course will overview the tools,
technologies and approaches which enable Si photonics to empower the
co-packaged optics initiatives pursued by the industry presently. The
capabilities offered by existing Si photonics dictate, to a large extent, the
advantages offered by co-packaged optics to the CMOS eco-system. Abilities
for co-packaged topics to positively fuel scaling system in a package (SiP)
by enhancing the interconnection density will be used as an example in this
course. This comprehensive course aims to
provide a thorough exploration of the fundamental tools, cutting-edge
technologies, and innovative approaches that underpin the remarkable
potential of Silicon (Si) photonics in driving and supporting the ongoing
co-packaged optics initiatives within the current industry landscape. As the
industry places increasing emphasis on co-packaged optics as a strategic
direction, understanding the intricacies of Si photonics becomes pivotal, as
its capabilities and functionalities wield a significant influence over the
advantages that co-packaged optics can bring to the broader CMOS ecosystem. Who Should Attend: The goal of this course is to
provide the participants with a multifaceted analysis of Si photonics,
examining its foundational principles, engineering intricacies, and diverse
applications. By grasping the core attributes of Si photonics, course
participants will gain a profound insight into the pivotal role it plays in
shaping the co-packaged optics landscape. One noteworthy aspect that will be
highlighted is how the inherent capabilities of Si photonics serve as a
linchpin for the advantages conferred by co-packaged optics. This
relationship will be elucidated through illustrative examples, such as the
way co-packaged optics can significantly augment the scalability of Systems
in Package (SiP) through heightened interconnection density. Through a
systematic exploration of these interconnected concepts, participants will
not only foster a comprehensive understanding of Si photonics and co-packaged
optics but also develop a discerning perspective on how these elements
synergistically contribute to the evolution of modern packaging technologies.
By the course's conclusion, attendees will be equipped with not only
theoretical knowledge but also practical insights that can be harnessed in
real-world scenarios, enabling them to make informed decisions and
innovations in the dynamic realm of co-packaged optics and Si photonics. As
the industry landscape continues to be shaped by rapid advancements, this
course stands as an invaluable resource for those seeking to navigate the
intricate interplay between Si photonics and co-packaged optics, ultimately
empowering them to drive forward advancements in system integration,
interconnectivity, and performance optimization. |
|
Instructor Biography: Amr S. Helmy is a professor in the
department of electrical and computer engineering at the University of
Toronto. Prior to his academic career, Amr held a position at Agilent
Technologies - UK, between 2000 and 2004. At Agilent his responsibilities
included developing lasers and monolithically integrated optoelectronic
circuits. He received his Ph.D. and M.Sc. from the University of Glasgow with
a focus on photonic integration technologies, in 1999 and 1995
respectively. His research interests include
photonic device physics, with emphasis on plasmonic nanostructures, nonlinear
and quantum photonics addressing applications in information processing /
sensing, and data communications. Amr is an active volunteer and leader of
the IEEE Photonics Society, currently serving as an Elected Member of the
Society’s Board of Governors and as a Distinguished Lecturer. He was also the
recipient of the Society’s 2019 Distinguished Service Award. |
|
Design-on-Simulation
Technology for Advanced Packaging Reliability Life Prediction |
|
Course Objective and
Outline: The electronic packaging (EP)
community has widely used Design-on-Simulation (DoS) technology for designing
a new packaging structure. Still, it has encountered some challenges in
ensuring a trustable simulation result. AI/machine learning approaches can be
combined with DoS to solve this uncertainty. This course will use wafer-level
packaging (WLP) to illustrate the solution methodology and procedure,
including the FE model, mechanics theories, controlled mesh size validation,
large database generation, and AI training performance of different machine
learning algorithms. This talk will also describe how to combine AI and
finite element simulation to estimate the reliability life of wafer-level
packaging and obtain the best structure combination of each packaging
component. This course will cover the following topics: (1) Finite element
simulation, (2) 2D/3D model, (3) Material constitutive equations, (4) Mesh
size control concept, (5) Simulation theory/materials/model validation
procedure, (6) Solder joint reliability life cycle prediction empirical
equations, (7) AI-Assisted DoS. Who Should Attend: This course aims to provide students
and engineers with a comprehensive understanding of how to properly combine
mechanics theories, constitution equations of material, finite-element
modelling, and reliability life prediction empirical equations to estimate
the reliability life cycle of area array type advanced packaging. Attendees
are encouraged to bring topics and technical issues from their past, present,
and future job functions for group discussions. |
|
Instructor Biography: Professor K. N. Chiang received his
PhD from the Georgia Institute of Technology, USA. He is the Chair Professor
at the National Tsing Hua University in Hsinchu, Taiwan. After graduating
from Georgia Tech, he worked four years as a senior researcher at MSC/NASTRAN,
a world-famous finite element system. From 2010 to 2013, he served as General
Director of the National High-Performance Computing Center, which is the
National Strategic Research Center of Taiwan. He has received outstanding
research awards from the Ministry of Science and Technology of Taiwan three
times and has published more than 450 technical papers in international
journals and conference proceedings. He has been granted more than 50
invention patents. Among the major awards Professor Chiang received are the
Excellence in Mechanics Award from ASME (2022) and the Outstanding Sustained
Technical Contribution Award (2020) from IEEE-EPS. Currently, he is
Editor-in-Chief of the Journal of Mechanics (SCI), Academic Editor of
Materials (SCI), and Associate Editor of the Journal of Electronic Packaging
(SCI). He is an IEEE, ASME, STAM, and IMAPS Fellow. And an academician of the
International Academy of Engineering (IAE). He has made significant achievements
in simulation-based science and technology. He successfully combined
simulation design with artificial intelligence technology and applied it
effectively to semiconductor-related designs. His technology has greatly
reduced product development time and development costs. He has worked with
many major electronic packaging, semiconductor and LED companies such as
ACET, TSMC, MediaTek, UMC, EPISTAR, VIA, Powertech Technology, etc. |
|
Automotive
Electronics Reliability – Challenges and Opportunities |
|
Course Objective and
Outline: The modern car has increased
semiconductor content and dollar value. Semiconductors enable the
majority of innovations in automotive. The increased emphasis on
autonomous driving and the electrification of vehicles has resulted in
enormous changes for semiconductors and packaging. The design,
materials, and reliability strategies for automotive electronics will be
presented. Electronics are increasingly being used in automotive
platforms for various mission-critical and safety-critical activities, such
as guidance, navigation, control, charging, sensing, and operator
interaction. Over the last two decades, automotive platforms have
expanded to incorporate hybrid and fully electric vehicles. Much of the
electronics is located under the car’s hood or in the trunk, where temperatures
and vibration levels are far higher than in consumer office
applications. During the vehicle’s use-life, electronics in the
automotive underhood may be exposed to sustained high temperatures of
125-150°C for extended periods. The Automotive Electronics Council
(AEC) has graded electronics for automotive purposes into four categories:
grade 0, grade 1, grade 2, and grade 3. Grade-0 components have the
most demanding criteria of the four grade categories, with predicted power
temperature cycling ranging from -40°C to +150°C for 1000 cycles and ambient
temperature cycling ranging from -55°C to +150°C for 2000 cycles.
Furthermore, the grade-0 components are expected to be capable of sustaining
high-temperature storage for 1000 hours at 175°C. With the introduction
of new packaging architectures, packaging applications have continued to
evolve, allowing for powerful computing on mobile automobile platforms.
New materials and integration technologies have also emerged, allowing for
tighter integration of electronics sensing and processing into the structural
characteristics of the vehicle. The automobile platform faces a series
of constraints particular to the real-time context for enabling sophisticated
functionality. Specifically, the course
will encompass the following topics: 1. Role
of electronics on the automotive platform 2. Automotive
environments 3. Zero-Defects 4. Second-Level
Solder Interconnect Design Considerations 5. Copper
Wirebond Interconnects 6. Advanced
Packaging Interfaces 7. Vibration
Effects 8. Sustained
High Temperature and Wide Thermal Extremes 9. Corrosion
Propensity 10. Accelerated
Testing Who Should Attend: The goal of the course is to provide
the students with a comprehensive understanding of the materials and
reliability considerations in the design of electronics for operation in the
automotive platform. The course is intended to have an intermediate
degree of difficulty to serve as an introduction for engineers and managers
looking to design electronics for operation in the automotive
underhood. |
|
Instructor Biography: Pradeep Lall is the MacFarlane Endowed Distinguished
Professor and Alumni Professor with the Department of Mechanical
Engineering. He is the Director of the NSF-CAVE3 Electronics Research
Center at Auburn University. He holds Joint Courtesy Appointments in
the Department of Electrical and Computer Engineering and the Department of
Finance. He is a member of the technical council and academic co-lead
of automotive TWG and asset monitoring TWG of NextFlex Manufacturing
Institute. He is the author and co-author of 2-books, 15 book chapters,
and over 900 journal and conference papers in the field of electronics
reliability, manufacturing, safety, testing, energy efficiency, and
survivability. Dr. Lall is a fellow of the ASME, a fellow of the IEEE,
a Fellow of NextFlex Manufacturing Institute, and a Fellow of the Alabama
Academy of Science. He is a recipient of the SEMI Flexi R&D
Achievements Award for landmark contributions to Additive Printed
Electronics, ASME Avram Bar-Cohen Memorial Medal, IEEE Biedenbach Outstanding
Engineering Educator Award, Auburn University Research Advisory Board’s
Advancement of Research and Scholarship Achievement Award, IEEE Sustained
Outstanding Technical Contributions Award, NSF-IUCRC Association’s Alex
Schwarzkopf Award, Alabama Academy of Science Wright A, Gardner Award, IEEE
Exceptional Technical Achievement Award, ASME-EPPD Applied Mechanics Award,
SMTA’s Member of Technical Distinction Award, Auburn University’s Creative
Research and Scholarship Award, SEC Faculty Achievement Award, Samuel Ginn
College of Engineering Senior Faculty Research Award, Three-Motorola
Outstanding Innovation Awards, Five-Motorola Engineering Awards, and over
Forty Best-Paper Awards at national and international conferences. Dr.
Lall is the founding faculty advisor for the SMTA student chapter at Auburn
University and a member of the editorial advisory board for SMTA
Journal. |