Dr Gamal Refai-Ahmed, Life Fellow ASME, Fellow IEEE, Fellow Canadian Academy of Engineering, is Xilinx Fellow and Chief Thermo-Mechanical Architect. He obtained the Ph.D. degree in Mechanical Engineering from the University of Waterloo. He has been recognized as one of the global technology leaders of thermal management through his numerous publications (more than 100 publications) and patents & patents pending US (more than 60) and International (more than 120). His contributions are seen in several generations of both GPU and FPGA products. State University of New York, Binghamton University awarded him the Innovation Partner Award for his industrial role with Binghamton University. Gamal is the recipient of the 2008 excellent thermal management award, 2010 Calvin Lecture and 2013 K16- Clock award in recognition for his scientific contributions and leadership of promoting the best electronics packaging engineering practice. In 2014, Gamal received the IEEE Canada R. H. Tanner Industry Leadership for sustained product development and industrial innovation leadership. In 2016, ASME awarded Gamal the ASME Service Award. In continuation to Dr Refai’s contributions to the best engineering practice, the State University of New York at Binghamton awarded him the Presidential University medal in 2019, the university’s highest recognition honour. Gamal was elected to IEEE Fellow for 2021.
Abstract: For several decades, microelectronic industries and relevant Academic communities have expended a tremendous effort developing packages in accordance with Moore's law, leading to not only many breakthroughs and revolution in packaging technologies, but also repetitive efforts addressing traditional problems. In recent years, the push into the Nano electronic era is resulting in an ever-increasing awareness of R&D efforts and business drivers to speed up the development and application of "more than Moore", all of which are based upon or derived from silicon technologies, but do not scale with Moore's law. For the optimized performance of Silicon packages, most of the academia-based publications often do not report the optimal configuration of the package considering the non-mathematical or mechanical and manufacturability constraints. With heterogeneous integration of different functionalities on a single chip that lead to ever-increasing localization of the heat, a major challenge in forward-looking roadmaps includes the thermomechanical reliability of the Silicon package. With traditional and commercially available cooling solutions approaching their useful limit, the focus must be shifted towards improving the interfacial resistance namely TIM1, TIM2 by establishing better contact. The total system package from the active die to the heatsink includes several subsystems sequentially arranged. Each of the subsystem’s performance are high interactive or dependent on the other. This article emphasizes that the interaction of the Die warpage with the elongation and adhesion of thermal interface materials (TIMs) plays a crucial role in determining the limits of Si packaging technologies. This can be seen clearly in a such package size of greater than 50mmx50mm which has a coplanarity more than 8 mil. This type of package can have be MCM, Chiplets, CoW0s, EMIB or monolithic. Furthermore, this manuscript also forecasts the different cooling techniques of data centers to enable the future higher performance Silicon.
Hybrid Bonding – State-of-the-Art and Upcoming Requirements by Paul Lindner
Abstract: Even though heterogeneous integration is not new to the industry, the packaging aspect has not been the focus on any of the PPAC metric. In recent years the system performance is getting more important, where heterogeneous integration and system-technology co-optimization (STCO) are the key building blocks for future devices, especially in high performance, AI and mobile applications. The presentation will give a short outlook into the session, including key building blocks of technology. Over the last decade fusion and hybrid bonding on wafer level has developed and is now readily available as unit process in most foundry and device manufacturers worldwide. In the current industry transformation away from optimization on planar devices towards system integration and towards 3D stacked devices, bonding technologies are playing a crucial role. While most devices such as image sensors or stacked memory have been designed specifically for 3D integration and bonding, the next technology transformation as a universal high density interconnect technology will also trigger a new integration process. Therefore, wafer-level as well as die-level hybrid bonding technologies are being developed and depending on interconnect density, chip size, system yield and cost, the best fit in terms of integration flow will be selected. In this presentation we will provide an overview on the current industry trends and technological developments both for wafer-to-wafer as well as die-to-wafer hybrid bonding. Key technology differentiators, integration scenarios are discussed with respect to the hybrid bonding schemes.
Innovative Copper Electrodeposition Solutions for High-Density Fanout Package Technology by Bryan Buckalew
Abstract: IC packaging technology has evolved in a quite diverse manner over the past decade, addressing both high-end and low-end applications, resulting in approaches such as package-on-package (PoP), high-density fan-out wafer-level package (HDFO), 3D IC integration with through-silicon via (TSV), and 2.5D with TSV-Si interposer. HDFO technology comprises conventional under-bump metallization (UBM) and pillar/micro-pillar, as well as new routing/connection applications such as fine-line redistribution layer (RDL) (sub 5x5μm), integrated via-RDL structures, and mega pillars (>100μm). These new applications drive fundamental challenges in electrodeposition. Fine-line RDL applications present challenges for both lithography and electrochemical deposition (ECD) processes. New electroplating technology is required to prevent physical degradation of the fine-line RDL. Cu undercut resulting from the Cu seed etch process can be minimized by using innovative electroplating technology to reduce the thickness of the Cu PVD seed layer. Thermal cracking of the Cu line has also been posed as a key integration challenge and can be overcome with grain engineering of the Cu ECD film. Many of the current HDFO approaches include the adoption of multi-layer RDL which are fabricated from low dielectric polymer passivation layers and Cu ECD lines. Multi-layer RDL patterns can result in significant topography variation, which can impact other process integration challenges such as control of critical dimensions (CDs). To minimize topography variation, a new ECD reactor design is used to provide ultra-uniform Cu ECD. Mega pillars consist of 180-220 mm (200μm average) Cu thickness while standard Cu pillar applications typically vary between 20 and 40μm (30μm average) thickness. The process of plating large features employed as interconnects often encounters mass transport limitations that can curtail the deposition rate. Convection of the electrolyte above the surface of the photoresist, which is largely influenced by the ECD reactor design, is shown to have a pronounced impact on fill times over the range of feature dimensions. Furthermore, some integration requirements for mega pillars warrant extremely high within-die uniformities and flat bump shape. Attaining such high-quality plating performance can greatly minimize the downstream planarization requirements. This presentation will focus on new innovations in Cu ECD processes for fine line RDL, multi-layer RDL, and mega pillar to enable HDFO technology.
Burn-in testing (bit): Predictive Modeling Enables Improving It by Suhir Ephriam
Ephraim Suhir is on the faculty of the Portland State University, Portland, OR, USA, Technical University, Vienna, Austria and James Cook University, Queensland, Australia. He is also CEO of a Small Business Innovative Research (SBIR) ERS Co. in Los Altos, CA, USA, is Foreign Full Member (Academician) of the National Academy of Engineering, Ukraine (he was born in that country); Life Fellow of the Institute of Electrical and Electronics Engineers (IEEE), the American Society of Mechanical Engineers (ASME), the Society of Optical Engineers (SPIE), and the International Microelectronics and Packaging Society (IMAPS); Fellow of the American Physical Society (APS), the Institute of Physics (IoP), UK, and the Society of Plastics Engineers (SPE); and Associate Fellow of the American Institute of Aeronautics and Astronautics (AIAA). Ephraim has authored 450+ publications (patents, technical papers, book chapters, books), presented numerous keynote and invited talks worldwide, and received many professional awards, including the 1996 Bell Laboratories Distinguished Member of Technical Staff (DMTS) Award (for developing effective methods for predicting the reliability of complex structures used in AT&T and Lucent Technologies products), and 2004 ASME Worcester Read Warner Medal (for outstanding contributions to the permanent literature of engineering and laying the foundation of a new discipline “Structural Analysis of Electronic Systems”). Ephraim is the third “Russian American”, after S. Timoshenko and I. Sikorsky, who received this prestigious award. His most recent awards are the 2019 IEEE Electronic Packaging Society (EPS) Field award for seminal contributions to mechanical reliability engineering and modelling of electronic and photonic packages and systems and the 2019 Int. Microelectronic Packaging Society’s (IMAPS) Lifetime Achievement award for making an exceptional, visible, and sustained impact on the microelectronics packaging industry and technology.
Abstract: The objective of this analysis is to explore what could be done to better understand the physics of and eventually to improve the burn-in testing (BIT) technology in electronic manufacturing. Three predictive analytical (“mathematical”) models are developed and applied. The model based on the analysis of the infant mortality portion (IMP) of the (non-random) bathtub curve (BTC) suggests that the time derivative of the failure rate at the beginning of this portion could be viewed as a suitable criterion (“figure of merit”) to answer the basic question, “to BIT or not to BIT?”, of the BIT undertaking. Clearly, if this derivative is zero, the IMP of the BTC is parallel to the time axis, so that the IMP simply does not exist, and no BIT is necessary. In another extreme case, when this derivative is significant (with a “minus” sign, of course), the IMP of the BTC clings to the vertical, failure-rate axis. Although the undesirable “freaks” do exist in such a situation, they could be easily eliminated by a short and low-level BIT. It is assumed that the “unfavorable” material degradation, physics-of-failure, related failure rate (PFR), which increases with time, do not play a role during this initial stage of the IMP of the BTC and is not considered. Only the “favorable”, statistic-of-failure related failure rate (SFR) that decreases with time is taken into account in this analysis. The model based on the analysis of the random failure rate (RFR) of the numerous mass-produced components that the manufactured product of interest is comprised of suggests that the above time derivative is, in effect, the variance of the RFR of these components. Their actual failure rates are typically unknown, and could very well vary in a very wide range, from zero to infinity. It is shown that the non-random SFR can be determined from the probability distributions of the random RFR. Finally, it is demonstrated that the model based on the multi-parametric Boltzmann-Arrhenius-Zhurkov (BAZ) equation can be effectively employed to establish the BIT’s adequate duration and level, if this failure-oriented-accelerated-testing (FOAT) is found to be necessary. The general concepts are illustrated by calculated data. It is concluded that predictive modeling should always precede the actual BIT and that analytical (“mathematical”) modeling should always complement computer simulations. The future work should be focused on the experimental validation and possible extension of the results and recommendations of this analysis and, hopefully and ultimately, on developing practical and effective BIT procedures
On-Demand technology Talks
Thermal Management challenges for Advance Packaging in HPC/AI/ML by Dr. Andy C. Mackie
Abstract: The high-performance computing (HPC) module and AI market is seeing some enormous simultaneous changes. The compute needs of XPU and tensor processors are causing die area to grow, with higher areal power density, and HBM DRAM stacks are now located immediately adjacent to the processor. The paper discusses how metallic thermal interface materials are providing the low thermal resistance, high reliability and flexibility for advanced compute modules and systems, in both TIM1 (die-lid), TIM 2 (lid-heatsink) and TIM 0 (1.5) (die to heatsink) applications. Reflowed indium as a TIM1 has a nearly two-decade performance record in high volume production, where a combination of CTE matching and very high relative bulk thermal conductivity is highly advantageous. This presentation will discuss the latest developments on indium and other metal alloys as known good solderable solutions that have demonstrated very high bulk thermal conductivity, relative to more common polymer TIMs for TIM1 applications, as well illustrating engineered variations of indium alloys that do not require a solder reflow process, eliminating manufacturing process steps. Discussion also includes metallic TIMs designed for use in TIM0 (TIM1.5) applications with the compression inherent in heat sink attachment with mechanical retention. Novel liquid-metal-based solutions are also under development, and the paper will describe some ways in which gallium alloys are providing ways to resolve some of the conflicting requirements (such as pressure and thinned die and reliability) of emerging applications.
Memory Packaging Trends by Emilie Jolivet
Abstract: Memory is a critical market in modern data-centric societies and is driven by important megatrends, including mobility, cloud computing, artificial intelligence (AI), and the internet of things (IoT). All these are fuelling the “data-generation explosion” and are responsible for a robust growth in memory-bit demand. The memory packaging market follows the same trends that rule the stand-alone memory market and will benefit from the robust growth of memory-bit demand and from the ongoing memory-wafer capacity expansion. Different from the stand-alone memory market that is characterized by strong price volatility, the memory packaging market is less volatile, since most of the business is carried out internally by memory IDMs. In 2020, we estimate that less than 30% of the memory packaging revenue is generated by OSATs.
Memory Packaging in
China is a key business opportunity for OSATs: the two rising memory players in
China – YMTC (NAND) and CXMT (DRAM) – do not have experience in
assembly/packaging and must outsource all their packaging to OSATs. We estimate
that the OSATs’ business opportunity related to these Chinese memory players
can grow from <$100M in 2020 to ~$1.1B in 2026 (CAGR20-26 ~55%). Wirebond is the most common memory packaging
technology. It accounts for >99% of NAND packaging revenues and nearly 100%
of mobile DRAM (LPDDR). Packaging for PC and server DRAM has been progressively
migrating from wirebond to flip chip. The adoption of flip-chip packaging with
short interconnects – suitable for low-latency data transfer – will be
essential to fully exploit the potential of DDR5 and subsequent DRAM
generations. With the ongoing slowdown
of Moore’s Law and the rise of new advanced packaging techniques, back-end
processing has gained more and more importance, and several semiconductor
companies are now leveraging on it – rather than on the front-end – to improve
the performance, the compactness and the number of functionalities of their IC
products. Heterogenous integration techniques (e.g., TSMC’s SoIC) and chiplet
architectures enabled by novel stacking/bonding approaches have become the
must-follow approaches to increase the performance of computing systems through
a tight integration of logic and memory building blocks.